대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

Twin-well Non-epitaxial CMOS Substrate에서의 노이즈 분석을 위한 Substrate Resistance 및 Guard-ring 모델링

A Substrate Resistance and Guard-ring Modeling for Noise Analysis of Twin-well Non-epitaxial CMOS Substrate

  • 김봉진 (포항공과대학교 아날로그 집적 회로 시스템 연구실) ;
  • 정해강 (포항공과대학교 아날로그 집적 회로 시스템 연구실) ;
  • 이경호 (포항공과대학교 아날로그 집적 회로 시스템 연구실) ;
  • 박홍준 (포항공과대학교 아날로그 집적 회로 시스템 연구실)
  • 발행 : 2007.04.25
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초록

[ $0.35{\mu}m$ ]twin-well non-epitaxial CMOS 공정에서의 substrate noise에 의한 아날로그 회로의 성능 저하를 예측하기 위하여 substrate 저항을 모델링하였다. Substrate 저항 모델 방정식은 P+ guard-ring isolation에 적용되어 측정값과 일치함을 확인하였다. Substrate 저항을 네 가지 형태로 구분하고 각각에 대하여 semi-empirical 모델 방정식을 확립하여, 측정값과 비교하여 rms 오차가 10% 미만이 되었다. 이 substrate 저항 모델을 guard-ring에 의한 isolation 구조에 적용하기 위하여 모델 방정식과 ADS(Advanced Design System) 회로 시뮬레이션에 의한 결과와 Network Analyzer의 측정 결과를 비교하였고, 비교적 잘 일치함을 확인하였다.

The substrate resistance is modeled to estimate the performance degradation of analog circuits by substrate noise in a $0.35{\mu}m$ twin-well non-epitaxial CMOS process. The substrate resistance model equations are applied to the P+ guard-ring isolation structure and a good match was achieved between measurements and models. The substrate resistance is divided into four types and a semi-empirical model equation is obtained for each type of substrate resistance. The rms(root-mean-square) error of the substrate resistance model is below 10% compared with the measured resistance. To apply this substrate resistance model to the P+ guard ring structure, ADS(Advanced Design System) circuit simulation results are compared with the measurement results using Network Analyzer, and relatively good agreements are obtained between measurements and simulations.

키워드

참고문헌

  1. M. Xu, D. K. Su, D. K. Shaeffer, T. H. Lee, and B. A. Wooley, 'Measuring and modeling the effects of substrate noise on the LNA for a CMOS GPS receiver,' IEEE Journal of Solid-State Circuits, vol. 36, no. 3, pp. 473-485, March 2001 https://doi.org/10.1109/4.910486
  2. I. Rahim, I. Lim, J. Foerstner, and B. Y. Hwang, 'Comparison of SOI versus bulk silicon substrate crosstalk properties for mixed-mode IC's,' in Proc. IEEE Int. SOI Conf., 1992, pp. 170-171
  3. D. K. Su, M. Loinaz, S. Masui, and B. A. Wooley, 'Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits,' IEEE J. Solid State Circuits, vol. 28, pp. 420-429, April 1993 https://doi.org/10.1109/4.210024
  4. D. J. Allstot, S. Chee, S. Kiaei, and M. Shrivastawa, 'Folded source coupled logic vs. CMOS static logic for low-noise mixed-signal IC's,' IEEE Trans. Circuits and Syst.-I, vol. 40, pp. 553-563, Sept. 1993 https://doi.org/10.1109/81.244904
  5. Thomas A. Johnson, Ronald W. Knepper, Victor Marcello, Wen Wang, 'Chip Substrate Resistance Modeling Technique for Integrated Circuit Design,' IEEE Transactions on Computer-Aided Design, vol. CAD-3, no. 2, April 1984
  6. L. Deferm, C. Claeys, and G. J. Declerk, 'Twoand three-dimensional calculation of substrate resistance,' IEEE Trans. Electron Devices, vol. 35, pp. 339-351, March 1988 https://doi.org/10.1109/16.2460
  7. Simon Kristiansson, Shiva P. Kagganti, Tony Ewert, Fredrik Ingvarson, Jorgen Olsson, Kjell O. Jeppson, 'Substrate Resistance Modeling for Noise Coupling Analysis,' IEEE ICMTS, March 2003 https://doi.org/10.1109/ICMTS.2003.1197429
  8. Brian E. Owens, Sirisha Adluri, Patrick Birrer, Robert Shreeve, Sasi Kumar Arunachalam, Kartikeya Marayam, Terri S. Fiez, 'Simulation and Measurement of Supply and Substrate Noise in Mixed-Signal ICs,' IEEE Journal of Solid State Circuits, vol. 40, no. 2, February 2005 https://doi.org/10.1109/JSSC.2004.841039
  9. Kuntal Joarder, 'A simple approach to modeling cross-talk in integrated circuits,' IEEE Journal of Solid-State Circuits, vol. 29, pp.1212-1219, October 1994 https://doi.org/10.1109/4.315205