A Low Power PRAM using a Power-Dependant Data Inversion Scheme

전력-종속 데이터 반전 기법을 이용한 저전력 상변환 메모리

  • Yang, Byung-Do (School of Electrical and Computer Engineering, Chungbuk National University)
  • 양병도 (충북대학교 전기전자컴퓨터공학부)
  • Published : 2007.11.25

Abstract

A low power PRAM using a power-dependant data inversion (PDI) scheme is proposed. The PRAM consumes large write power because large write currents are required during long time. Also, the power consumptions for storing #1# and #0# are different. The PDI circuit compares the power consumptions to store the original data and its inverted data, and then it stores the less power consuming data. Although the PDI scheme needs an additional inversion bit per data, the maximum and average powers of the PDI can be under 50% and 37.5% of the conventional write scheme, respectively. The average power for storing 8bit data is under 41%, due to the inversion bit. The 1K-bit PRAM chip with 128$\times$8bits was implemented with a 0.8${\mu}m$ CMOS technology with a 0.5${\mu}m$ GST cell.

Keywords

References

  1. Hyung-rok Oh, et al., 'Enhanced Write Performance of a 64-Mb Phase-Change Random Access Memory,' IEEE J. Solid-State Circuits, Vol. 41, No. 1, pp. 122-126, Jan. 2006 https://doi.org/10.1109/JSSC.2005.859016
  2. Woo Yeong Cho, et al., 'A $0.18-{\mu}m$ 3.0-V 64-Mb Nonvolatile Phase-Transition Rrandom Access Memory (PRAM),' IEEE J. Solid-State Circuits, Vol. 40, No. 1, pp. 293-300, Jan. 2005 https://doi.org/10.1109/JSSC.2004.837974
  3. Y. N. Hwang, et al, 'Full integration and reliability evaluation of phase-change RAM based on $0.24-{\mu}m$-CMOS technologies,' Symp. VLSI Technology Dig., pp. 173-174, June 2003