Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

Effective Power/Ground Network Design Techniques to suppress Resonance Effects in High-Speed/High-Density VLSI Circuits

고속/고밀도 VLSI 회로의 공진현상을 감소시키기 위한 효율적인 파워/그라운드 네트워크 설계

  • Ryu Soon-Keol (Dept. of Electrical & Computer Engineering, Hanyang University) ;
  • Eo Yung-Seon (Dept. of Electrical & Computer Engineering, Hanyang University) ;
  • Shim Jong-In (Dept. of Electrical & Computer Engineering, Hanyang University)
  • 류순걸 (한양대학교 전자컴퓨터공학부) ;
  • 어영선 (한양대학교 전자컴퓨터공학부) ;
  • 심종인 (한양대학교 전자컴퓨터공학부)
  • Published : 2006.07.01
Download PDF
⟨ Previous Next ⟩

Abstract

This paper presents a new analytical model to suppress RLC resonance effects which inevitably occur in power/ground lines due to on-chip decoupling capacitor and other interconnect circuit parasitics (i.e., package inductance, on-chip decoupling capacitor, and output drivers, etc.). To characterize the resonance effects, the resonance frequency of the circuit is accurately estimated in an analytical manner. Thereby, a decoupling capacitor size to suppress the resonance for a suitable circuit operation is accurately determined by using the estimated resonance frequency. The developed novel design methodology is verified by using $0.18{\mu}m$ process-based-HSPICE simulation.

본 논문에서는 온칩 디커플링 커패시터에 의한 파워/그라운드 라인에서의 RLC 공진현상을 감소시키기 위한 해석적인 모델을 제시한다. 패키지 인덕턴스와 온칩 디커플링 커패시터 및 출력 드라이버로 인하여 형성되는 RLC 공진 회로의 공진주파수를 정확하게 예측하였다. 예측된 공진주파수를 이용하여 회로 동작에 필요한 적절한 디커플링 커패시터의 크기를 결정할 수 있다. 본 논문에서 제시한 공진현상을 감소시킬 수 있는 새로운 설계 방법의 타당성은 $0.18{\mu}m$ 공정 HSPICE 모텔을 사용한 시뮬레이션을 통하여 검증하였다.

Keywords

References

  1. S. Lin, and N. Chang, 'Challenges in power-ground integrity,' in IEEE International Conference on Computer-Aided Design, 2001, pp. 651-654 https://doi.org/10.1109/ICCAD.2001.968730
  2. P. Heydari, and M. Pedram, 'Ground Bounce in' Digital VLSI Circuits,' IEEE Trans. VLSI Syst., vol. 11, pp. 180-193, April 2003 https://doi.org/10.1109/TVLSI.2003.810785
  3. H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI. Addison-Wesley, 1990
  4. D. T. Cox et al., 'VLSI performance compensation for off-chip drivers and clock generation,' in IEEE Custom Integrated Circuits Conference, 1989, pp. 14.3.1-14.3.4 https://doi.org/10.1109/CICC.1989.56752
  5. K. Leung, 'Controlled slew rate output buffer,' in IEEE Custom Integrated Circuits Conference, 1988, pp. 5.5.1-5.5.4 https://doi.org/10.1109/CICC.1988.20805
  6. C. Huang, Y,Yang and J.L.Prince, 'A simultaneous switching noise design algorithm for leadframe packages with or without ground plane.' IEEE T. on Components, Packaging, and Manufacturing Technology-Part B 19(1), pp. 15-22, Feb. 1996 https://doi.org/10.1109/96.486478
  7. A. J. Rainal, 'Eliminating inductive noise of external chip connections.' IEEE J. of SolidState Circuits 29(2), pp. 126-129, Feb. 1994 https://doi.org/10.1109/4.272116
  8. P. Larsson, 'di/dt noise in CMOS integrated circuits,' Analog Integrated Circuits and Signal Processing, no. 1/2, pp. 113-130, Sept. 1997 https://doi.org/10.1023/A:1008255029409
  9. B. Young, Digital Signal Integrity. Prentice Hall, 2001
  10. R. Senthinathan and J. L. Prince, 'Simultaneous switching ground noise calculation for packaged CMOS devices,' IEEE J. Solid-Sate Circuits, vol. 26, pp. 1724-1728, Nov. 1991 https://doi.org/10.1109/4.98995
  11. A. Vaidyanath, et al., 'Effect of CMOS driver ？loading conditions on simultaneous switching noise,' IEEE Trans. Comp., Packag., Manufact. Technol., vol. 17, pp. 480-485, Nov. 1994 https://doi.org/10.1109/96.338712
  12. S. R. Vemuru, 'Accurate simultaneous switching noise estimation including velocity-saturation effects,' IEEE Trans. Comp. Packag., Manufact. Technal. B, vol. 19, pp. 344-349, May 1996 https://doi.org/10.1109/96.496038
  13. Y. Eo, et al., 'New simultaneous switching noise analysis and modeling for high-speed and high-density CMOS IC package design,' IEEE Trans. Adv. Packag., vol. 23, pp. 303-312, May 2000 https://doi.org/10.1109/6040.846649
  14. A. Kabbani and A. J. Al-Khalili, 'Estimation of ground bounce effects on CMOS circuits,' IEEE Trans. Comp. Packag., Manufact. Technol., vol. 22, pp. 316-325, Jun. 1999 https://doi.org/10.1109/6144.774752
  15. K Bathey et al., 'Noise computation in single chip packages,' IEEE Trans. Comp., Packag., Manufact. Technol. B, vol. 19, pp. 350-360, May 1996 https://doi.org/10.1109/96.496039
  16. T. Gabara, W. C. Fischer, J. Harrington, and W. W. Troutman, 'Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffer,' IEEE J. Solid State Circuits, vol. 32, pp. 407-418, Mar. 1997 https://doi.org/10.1109/4.557639
  17. P. Larsson, 'Resonance and damping in CMOS circuits with on-chip decoupling capacitance,' IEEE Trans. Circuits Syst., vol. 45, pp. 849-858, Aug. 1998 https://doi.org/10.1109/81.704824
  18. M. Ingels and M. Steyaert, 'Design strategies and decoupling techniques for reducing the effects of electrical interference in mixed-mode IC's,' IEEE J. Solid-State Circuits, vol. 32, pp. 1136-1141, July 1997 https://doi.org/10.1109/4.597306
  19. Artice M. Davis, Linear Circuit Analysis. PWS Publishing Company, 1998
  20. X. Aragones, et al., Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs. Kluwer Academic Publishers, 1999