Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A new bit line structure minimizing coupling noise for DRAM

DRAM의 비트 라인 간 커플링 노이즈를 최소화한 오픈 비트 라인구조

  • Oh, Myung-Kyu (Department of Computer & Communication Engineering, Graduate School, Chungbuk University) ;
  • Jo, Kyoung-Rok (Department of Computer & Communication Engineering, Graduate School, Chungbuk University) ;
  • Kim, Sung-Sik (Department of Computer & Communication Engineering, Graduate School, Chungbuk University)
  • 오명규 (충북대학교 정보통신공학과) ;
  • 조경록 (충북대학교 정보통신공학과) ;
  • 김성식 (충북대학교 정보통신공학과)
  • Published : 2004.06.30
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Abstract

This paper describes a novel bit line structure to minimize coupling noise induced by coupling capacitance between bit lines. In DRAMs coupling capacitance is inherently present bit lines. As in submicron process the bit line space gets narrower. bit line coupling capacitance increases and this increased coupling capacitance sharply raises cross-talk noise. In this paper using different layers of metal for adjacent bit lines has been tested to reduces cross-talk noise and a novel bit line structure capable of reducing capacitance is introduced and verified.

본 논문에서는 비트라인간의 커플링 캐패시터에 의해서 발생하는 커플링 노이즈를 최소화 한 비트 라인구조를 제시하였다. DRAM의 비트 라인간에는 반드시 커플링 캐패시터가 존재한다. 서브마이크론 공정에서는 비트 라인간의 간격이 줄어듦으로써 비트 라인간의 커플링 캐패시터는 증가하게 되고 이 커플링 캐패시터에 의해서 크로스 토크잡음이 급격히 증가한다. 본 논문에서는 비트라인간의 크로스 토크잡음을 줄이기 위해 인접한 비트 라인에 사용하는 금속배선의 층을 서로 다르게 함으로써 비트라인간의 캐패시터를 줄인 새로운 비트 라인구조를 제안하고 검증한다.

Keywords

References

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