Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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Design of $GF(3^m)$ Current-mode CMOS Multiplier

$GF(3^m)$상의 전류모드 CMOS 승산기 설계

  • 나기수 (인하대학교 전자공학과) ;
  • 변기녕 (가톨릭 대학교 정보통신전자공학부) ;
  • 김흥수 (인하대학교 전자공학과)
  • Published : 2004.07.01
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Abstract

In this paper, we discuss on the design of a current mode CMOS multiplier circuit over $GF(3^m)$. Using the standard basis, we show the variation of vector representation of multiplicand by multiplying primitive element α, which completes the multiplicative process. For the $GF(3^m)$ multiplicative circuit design, we design GF(3) adder and multiplier circuit using current mode CMOS technology and get the simulation results. Using the basic gates - GF(3) adder and multiplier, we build the $GF(3^m)$ multiplier circuit and show the examples for the case m=3. We also propose the assembly of the operation blocks for a complete $GF(3^m)$ multiplier. Therefore, the proposed circuit is easily extensible to other p and m values over $GF(p^m)$ and has advantages for VLSI implementation. We verify the validity of the proposed circuit by functional simulations and the results are provided.

본 논문에서는 $GF(3^m)$상의 전류모드CMOS 승산기의 설계에 관하여 논의한다. 피 승산항에 원시원소 α를 곱함으로써 나타나는 피 승산항의 변화를 표준기저 표현을 이용하여 수식으로 전개하였다. $GF(3^m)$ 승산 회로를 구성하기 위하여 전류모드 CMOS를 사용하여 GF(3)상의 가산기와 승산기를 설계하였고 시뮬레이션 결과를 보였다. 기본 게이트들을 이용하여 $GF(3^m)$ 승산기를 설계하였고 m=3인 경우에 대하여 예를 보였다. 본 논문에서 제안한승산회로는 그 구성이 블록의 형태로 이루어지므로 $GF(p^m)$ 상에서 p와 m에 대한 확장이 용이하며, VLSI 구현에 유리하다 할 수 있다. 본 논문에서 제안한승산회로를 타 승산회로와 비교하였고, 개선효과를 확인하였다.

Keywords

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