대한전기학회논문지:시스템및제어부문D (The Transactions of the Korean Institute of Electrical Engineers D)

대한전기학회 (The Korean Institute of Electrical Engineers)
권호 표지

PSA 기법에 근거한 생산라인상의 디지털 회로 보오드 검사전략에 대한 연구

A Study on the Test Strategy of Digital Circuit Board in the Production Line Based on Parallel Signature Analysis Technique

  • 고윤석 (남서울대학 전자정보통신공학부)
  • 발행 : 2004.11.01
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초록

The SSA technique in the digital circuit test is required to be repeated the input pattern stream to n bits output nodes n times in case of using a multiplexor. Because the method adopting a parallel/serial bit convertor to remove this inefficiency has disadvantage of requiring the test time n times for a pattern, the test strategy is required, which can enhance the test productivity by reducing the test time based on simplified fault detection mechanism. Accordingly, this paper proposes a test strategy which enhances the test productivity and efficiency by appling PAS (Parallel Signature Analysis) technique to those after analyzing the structure and characteristics of the digital devices including TTL and CMOS family ICs as well as ROM and RAM. The PSA technique identifies the faults by comparing the reminder from good device with reminder from the tested device. At this time, the reminder is obtained by enforcing the data stream obtained from output pins of the tested device on the LFSR(Linear Feedback Shift Resister) representing the characteristic equation. Also, the method to obtain the optimal signature analyzer is explained by furnishing the short bit input streams to the long bit input streams to the LFSR having 8, 12, 16, 20bit input/output pins and by analyzing the occurring probability of error which is impossible to detect. Finally, the effectiveness of the proposed test strategy is verified by simulating the stuck at 1 errors or stuck at 0 errors for several devices on typical 8051 digital board.

키워드

참고문헌

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