참고문헌
- H. B. Bakoglu, 'Circuits, interconnections and for VLSL,' Addsion-Wesley, 1990
- R. Senthinathan and J. L. Prince, 'Simultaneous switching ground noise calculation for packaged CMOS devices,' IEEE J. Solid-Sate Circuits, pp. 1724-1728, Nov. 1991 https://doi.org/10.1109/4.98995
- A. Vaidyanath, et al., 'Effect of CMOS driver loading conditions on simultaneous switching noise,' IEEE Trans. Comp. Packag. Technol. B, pp. 480-485, Nov. 1994 https://doi.org/10.1109/96.338712
- Li Ding and P. Mazumder, 'Accurate estimating simultaneous switching noises by using application specific device modeling,' in Proc. of ECE., Design, Automation and Test, pp.1038-1043, Mar. 2002 https://doi.org/10.1109/DATE.2002.998428
- S. R. Vemuru, 'Accurate simultaneous switching noise estimation including velocity-saturation effects,' IEEE Trans. Comp. Packag. Technol. B, pp. 344-349, May 1996 https://doi.org/10.1109/96.496038
- Y. Eo, et al., 'New simultaneous switching noise analysis and modeling for high-speed and high-density CMOS IC package design,' IEEE Trans. Adv. Packag., vol. 23, pp. 303 312, May 2000 https://doi.org/10.1109/6040.846649
- B. Kanigicherla, et al. 'Determination of optimum on-chip Bypass capacitor in CMOS VLSI system to reduce switching noise,' in Proc. of IEEE Symp. on Circuits and System, vol. 3, pp. 1724-1727, Jun. 1997 https://doi.org/10.1109/ISCAS.1997.621473
- J. Choi, et al., 'A methodology for the placement and optimization of decoupling capacitors for gigahertz systems', International Conf. on VLSI Design, pp. 156 161, Jan. 2000 https://doi.org/10.1109/ICVD.2000.812602
- P. Larsson, 'Resonance and damping in CMOS circuits with on-chip decoupling capacitance', IEEE Trans. Circuits Syst. I, vol. 45, pp. 849858, Aug. 1998 https://doi.org/10.1109/81.704824
- M. D. Pant, et al., 'On-Chip decoupling capacitor optimization using architectural level prediction', IEEE Trans. VLSI Syst., vol. 10, pp. 319 326, Jun 2002 https://doi.org/10.1109/TVLSI.2002.1043335
- H. H. Chen and et al., 'On-chip decoupling capacitor optimization for noise and leakage reduction,' in Proc. of IEEE Sympo. on Integrated Circuits and Systems Design, pp. 251-255, Sept. 2003 https://doi.org/10.1109/SBCCI.2003.1232837
- P. Heydari and M. Pedram, 'Ground bounce in digital VLSI circuits,' IEEE Tran. VLSI Syst., vol. 11, pp. 108-193, Apr. 2003 https://doi.org/10.1109/TVLSI.2003.810785