Soft Lithographic Approach to Fabricate Sub-50 nm Nanowire Field-effect Transistors

A soft-lithographic top-down approach is combined with an epitaxial layer transfer process to fabricate high quality III-V compound semiconductor nanowires (NWs) and integrate them on Si/SiO2 substrates, using MBE-grown ultrathin InAs as a source wafer. The channel width of the InAs nanowires is controlled by using solvent-assisted nanoscale embossing (SANE), descumming, and etching processes. By optimizing these processes, the NW width is scaled to less than 50 nm, and the InAs NWFETs has ${\sim}1,600cm^2/Vs$ peak electron mobility, which indicates no mobility degradation due to the size.