• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.2
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• pp.1-10
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• 1999

Direct extraction of FET's small signal model parameters needs predetermined parasitic elements usually obtained under forward cold FET conditionl This paper derives analytic intrinsic model for cold FET's and shows that normal cold FET condition can replace forward cold FET condition for extracting parasitic elements. Then, we track the error of hot FET's small signal model bounded by the cold FET condition and examine the validness of cold parasitic resistances by checking the existence of the error minimum.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.05a
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• pp.560-561
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• 2022

In this paper, current-voltage characteristics of various types of Nanosheet FET (NSFET) and FinFET are simulated with 3D device simulator. The threshold voltage and subthreshold swing extracted from the simulated current-voltage characteristics of NSFET and FinFET were compared. Both of threshold voltage and drain current of NSFET are higher than those of FinFET. The subthreshold voltage swing (SS) of NSFET is steeper than that of FinFET.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.10a
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• pp.121-122
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• 2022

In this paper, the device performance with the structure of Nanosheet FET (NSFET) and FinFET is simulated through a three-dimensional device simulator. Current-voltage characteristics of NSFET and FinFET were simulated with respect to channel doping concentrations, and the performance such as threshold voltage and subthreshold swing extracted from the current-voltage characteristics was compared. NSFET flows more drain current and has a higher threshold voltage in current-voltage characteristics depending on channel doping concentration than that of FinFET. The subthreshold voltage swing (SS) of NSFET is steeper than that of FinFET

• Proceeding of EDISON Challenge
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• 2017.03a
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• pp.448-452
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• 2017

단층 $MoS_2$와 단층 실리콘을 채널 물질로 사용한 TMD FET과 UTB FET의 소자 특성 분석 시뮬레이션을 진행하였다. TMD FET과 UTB FET의 채널과 oxide 두께를 변화시켜가며 각 각의 게이트 전압과 드레인 전류의 특성과 subthreshold swing 등을 분석하였으며, 채널과 oxide 두께가 얇을수록 단채널 효과가 줄어든다는 것을 알 수 있었다. 얇은 채널을 사용하는 트랜지스터의 최적 구동 조건은 채널과 oxide 층의 두께가 1 nm 정도 되어야 한다는 시뮬레이션 결과를 바탕으로 TMD FET과 UTB FET의 소자 특성을 상호 비교해 보았으며 TMD FET의 SS값이 더 좋다는 것을 확인할 수 있었다.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.301.2-301.2
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• 2014

집적회로의 밀도가 높이기 위해 단일 소자의 크기를 줄이는 과정에서 발생하는 소자의 성능 저하를 줄이기 위해 새로운 구조 및 구성 물질을 변경하는 연구가 활발하게 진행되고 있다. 기존의 평면 구조를 변형한 3차원 구조의 n-channel FinFet는 소자의 구성 물질을 바꾸지 않고도 쇼트 채널효과와 누설전류를 줄일 수 있다. 다양한 구조의 유전 물질을 응용한 n-channel FinFEET은 기존의 n-channel FinFET보다 소자의 크기를 줄일 수 있는 가능성을 제시하고 있다. FinFETs에 관한 많은 연구가 진행되어 왔지만, 유전체 물질을 이용한 n-channel FinFETs의 구조에 대한 연구는 매우 적다. 본 연구는 FinFET의fin channel 영역에 유전 물질을 삽입하여 그 영향을 분석한 연구이다. FinFET의 fin channel 영역에 유전 물질을 삽입하여 평면 구조의 MOSFET에서 fully depletion SOI 구조와 같은 동작을 하도록 만들었다. 유전 물질을 삽입한 FinFET 소자의 전기적 특성을 3차원 TCAD 시뮬레이션을 툴을 이용하여 계산하였다. 유전 물질을 삽입한 n-channel FinFET에서 전자 밀도와 측면 전계의 영향이 기존의 FinFET보다 좋은 특성을 확인하였다. 또한 유전물질을 삽입한 FinFETs은 subthershold swing, 누설전류, 소비전력을 줄여 주었다. 이러한 결과는 n-Channel FinFETs의 성능을 향상시키는데 많은 도움이 될 것이다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.11
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• pp.1170-1175
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• 2003

In this paper, the output power improvement of Push-Push FET DRO by adding the identical DR at the drain port as one used in the gate port, has been theoretically investigated. The investigation shows that the DR located between two microstrip lines locks the phase difference of two FET's outputs at 180 degree and improves the output power of Push-Push FET DRO. Since this effect can be used for correcting the impedance difference between two FETs output circuits and the electrical length error of the power combiner at the output circuit of Push-Push DRO, which may occur when fabricate the oscillator, the oscillator with an additional DR can be useful structure for fabricating oscillator.

• Electronics and Telecommunications Trends
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• v.38 no.6
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• pp.52-61
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• 2023

With semiconductor scaling approaching the physical limits, devices including CMOS (complementary metal-oxide-semiconductor) components have managed to overcome yet are currently struggling with several technical issues like short-channel effects. Evolving from the process node of 22 nm with FinFET (fin field effect transistor), state-of-the-art semiconductor technology has reached the 3 nm node with the GAA-FET (gate-all-around FET), which appropriately addresses the main issues of power, performance, and cost. Technical problems remain regarding the foundry of GAA-FET, and next-generation devices called post-GAA transistors have not yet been devised, except for the CFET (complementary FET). We introduce a CFET that spatially stacks p- and n-channel FETs on the same footprint and describe its structure and fabrication. Technical details like stacking of nanosheets, special spacers, hetero-epitaxy, and selective recess are more thoroughly reviewed than in similar articles on CFET fabrication.

• Applied Chemistry for Engineering
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• v.24 no.1
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• pp.1-9
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• 2013

As the medical paradigm is changing from disease treatment to disease prevention and an early diagonosis, the demand to develop techniques for the detection of minute concentrations of biomolecules is increasing. Among the various techniques to sense the minute concentration of biomolecules, the biosensors utilizing the matured semiconductor techniques are presented here. To understand such biosensors, the structure and working principle of a MOSFET (Metal-oxide-semiconductor field-effect transistor) which is the basic semiconductor device is firstly introduced, and then the ISFET (Ion sensitive FET), BioFET (Biologically modified FET), Nanowire FET, and IFET (Ionic FET) are introduced, and their applications to biomedical fields are discussed.

• ETRI Journal
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• v.39 no.1
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• pp.62-68
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• 2017

In this paper, we present the design and characterization analysis of a cascode GaN field-effect transistor (FET) for switching power conversion systems. To enable normally-off operation, a cascode GaN FET employs a low breakdown voltage (BV) enhancement-mode Si metal-oxide-semiconductor FET and a high-BV depletion-mode (D-mode) GaN FET. This paper demonstrates a normally-on D-mode GaN FET with high power density and high switching frequency, and presents a theoretical analysis of a hybrid cascode GaN FET design. A TO-254 packaged FET provides a drain current of 6.04 A at a drain voltage of 2 V, a BV of 520 V at a drain leakage current of $250{\mu}A$, and an on-resistance of $331m{\Omega}$. Finally, a boost converter is used to evaluate the performance of the cascode GaN FET in power conversion applications.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.4
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• pp.484-491
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• 2008

In this paper, we design and fabricate the L-band high speed pulsed HPA using LDMOS FET. And we propose the high voltage and high speed switching circuit for LDMOS FET. The pulsed HPA using LDMOS FET is simpler than using GaAs FET because it has a high gain, high output power and sin81e voltage supply. LDMOS FET is suitable for pulsed HPA using switching method because it has $2{\sim}3$ times higher maximum drain-source voltage(65 V) than operating drain-source voltage($V_{ds}=26{\sim}28\;V$). As results of test, the output peak power is 100 W at 1.2 GHz, the rise/fall time of output RF pulse are 28.1 ns/26.6 ns at 2 us pulse width with 40 kHz PRF, respectively.