• Journal of Korea Multimedia Society
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• v.12 no.2
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• pp.165-177
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• 2009

Embedded database systems (EDBMS) based on NAND flash memories are widely adopted for logging data on sensor nodes. Since write and erase operations of a flash memory are time consuming compared to read operations and wear memory cells, it is important to reduce these operations to enhance the EDBMS performance and to extend the memory life. In this paper, we propose a delayed write scheme to archive this goal. Proposed scheme stores updated parts of database pages into delayed write records to reduce the database page writes. By doing that, it decreases write and erase operations on a flash memory. Therefore, the proposed scheme enhances the logging performance of a write-intensive EDBMS on a sensor node and extends the flash memory life.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.45-50
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• 2007

This paper proposes a low power selective data write (SDW) scheme for a phase-change random access memory (PRAM). The PRAM consumes large write power because large write currents are required during long time. At first, the SDW scheme reads a stored data during write operation. And then, it writes an input data only when the input and stored data are different. Therefore, it can reduce the write power consumption to a half. The 1K-bit PRAM test chip with $128{\times}8bits$ is implemented with a $0.8{\mu}m$ CMOS technology with a $0.8{\mu}m$ GST cell.

• Journal of KIISE
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• v.43 no.2
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• pp.177-185
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• 2016

In this paper, we propose a hybrid write buffer architecture comprised of DRAM and NVRAM on SSD and a write buffer algorithm for the hybrid write buffer architecture. Unlike other write buffer algorithms, the proposed algorithm considers read pages as well as write pages to improve the performance of storage devices because most actual workloads are read-write mixed workloads. Through effectively managing NVRAM pages, the proposed algorithm extends the endurance of SSD by reducing the number of erase operations on NAND flash memory. Our experimental results show that our algorithm improved the buffer hit ratio by up to 116.51% and reduced the number of erase operations of NAND flash memory by up to 56.66%.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.262-269
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• 2005

Semiconductor scientists and engineers ideally desire the faster but the cheaper non-volatile memory devices. In practice, no single device satisfies this desire because a faster device is expensive and a cheaper is slow. Therefore, in this paper, we use heterogeneous non-volatile memories and construct an efficient hierarchy for them. First, a small RAM device (e.g., MRAM, FRAM, and PRAM) is used as a write buffer of flash memory devices. Since the buffer is faster and does not have an erase operation, write can be done quickly in the buffer, making the write latency short. Also, if a write is requested to a data stored in the buffer, the write is directly processed in the buffer, reducing one write operation to flash storages. Second, we use many types of flash memories (e.g., SLC and MLC flash memories) in order to reduce the overall storage cost. Specifically, write requests are classified into two types, hot and cold, where hot data is vulnerable to be modified in the near future. Only hot data is stored in the faster SLC flash, while the cold is kept in slower MLC flash or NOR flash. The evaluation results show that the proposed hierarchy is effective at improving the access time of flash memory storages in a cost-effective manner thanks to the locality in memory accesses.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.3
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• pp.336-340
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• 2010

Flash storages are prevalent as portable storage in computing systems. When we consider the detachability of Flash storage devices, data integrity becomes an important issue. To assure extreme data integrity, file systems synchronously write all file data to storage accompanying hot write references. In this study, we concentrate on the effect of hot write references on Flash storage, and we consider the effect of absorbing the hot write references via nonvolatile write cache on the performance of the FTL schemes in Flash storage. In 80 doing, we quantify the performance of typical FTL schemes for workloads that contain hot write references through a wide range of experiments on a real system environment. Through the results, we conclude that the impact of the underlying FTL schemes on the performance of Flash storage is dramatically reduced by absorbing the hot write references via nonvolatile write cache.

• Journal of KIISE
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• v.42 no.2
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• pp.169-176
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• 2015

The atomic write technique is a good solution to solve the problem of the double write buffer. The atomic write technique needs modified I/O subsystems (i.e., file system and I/O schedulers) and a special SSD that guarantees the atomicity of the write request. In this paper, we propose the writing unit aligned block allocation technique (for EXT4 file system) and the merge prevention of requests technique for the CFQ scheduler. We also propose an atomic write-supporting SSD which stores the atomicity information in the spare area of the flash memory page. We evaluate the performance of the proposed atomic write scheme in MariaDB using the tpcc-mysql and SysBench benchmarks. The experimental results show that the proposed atomic write technique shows a performance improvement of 1.4~1.5 times compared to the double write buffer technique.

• Journal of computational fluids engineering
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• v.13 no.1
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• pp.1-6
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• 2008

Direct Write Technologies are being utilized in various industrial fields such as antennas, engineered structures, sensors and tissue engineering. With Direct Write Technologies, producing features have the mesoscale range, from 1 to 100 microns. One form of the Direct Write Technologies is based on aerosol dynamics. The shape of deposited aerosols determine the form of products in the Direct Write Technology based on aerosol dynamics. To predict shape of deposited aerosol, a prediction model is created. In this study, we estimated Line-Width and Line-Thickness from the prediction model. Results of prediction model is valid from comparison with experimental results.

• The Transactions of the Korea Information Processing Society
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• v.3 no.4
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• pp.983-991
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• 1996

This paper proposes an improved write-piggybacking technique called hybrid write-piggybacking, and evaluates its performance. The performance of the proposed hybrid write-piggybacking technique is done through a trace-driven simulation using a model of a real disk system. The results of simulation show that the proposed hybrid write-piggybacking has better performance compared to the original write-piggybacking technique.

• Proceedings of the KIEE Conference
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• 2003.04a
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• pp.47-49
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• 2003

수직 기록 방식은 그 기록 방식의 차이로 인하여 수평 기록 방식에서 쓰여 오던 Write Head의 Design을 적용하였을 경우 기록 밀도를 높이는데 많은 문제점과 낮은 기록 밀도 상승률을 동반하게 된다. 따라서 수직 기록 방식의 자기 기록에서는 수직 기록 방식에 적합한 Write Head의 Design을 적용하여야만 한다. 본 논문에서는 3차원 유한요소법을 이용하여 수직 기록용 Write Head의 한 종류인 SPT Head(Single Pole Tip Head)를 최적 설계하여 그 Write Field의 특성을 분석 제시하였다. 또한 기록 Media의 차이에 따른 기록 특성을 분석하기 위하여 기존 Single Layer 방식과 SUL (Soft Magnetic Under layer)를 사용한 Double Layer 방식을 이용하였을 경우 SUL이 자기 기록에 미치는 영향에 대한 내용을 연구 분석하여 제시하였다.

• Proceedings of the Korean Powder Metallurgy Institute Conference
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• 2006.09a
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• pp.372-373
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• 2006

Modern business trends call for miniaturization of electronic systems. One of the major impedances in this miniaturization is the conductive and inductive components in chips and circuit boards. Direct Write Technology can write these soft magnetic materials, thus allowing for further miniaturization of inductor devices. Another obstacle in electronics fabrication is the size limitations of thick screen-printing and the material limitations in ink jet printing. Direct Write Technologies address both of these limitations by providing feature sizes less than 20 microns with a wide range of materials possibilities. A discussion of the application of these nano-particulate materials by Direct Write Technologies will be presented.