• Journal of Computing Science and Engineering
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• v.3 no.4
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• pp.195-215
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• 2009

Worst-case execution time (WCET) analysis is critical for hard real-time systems to ensure that different tasks can meet their respective deadlines. While significant progress has been made for WCET analysis of instruction caches, the data cache timing analysis, especially for set-associative data caches, is rather limited. This paper proposes an approach to safely and tightly bounding data cache performance by computing the worst-case stack distance of data cache accesses. Our approach can not only be applied to direct-mapped caches, but also be used for set-associative or even fully-associative caches without increasing the complexity of analysis. Moreover, the proposed approach can statically categorize worst-case data cache misses into cold, conflict, and capacity misses, which can provide useful insights for designers to enhance the worst-case data cache performance. Our evaluation shows that the proposed data cache timing analysis technique can safely and accurately estimate the worst-case data cache performance, and the overestimation as compared to the observed worst-case data cache misses is within 1% on average.

• Journal of Communications and Networks
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• v.6 no.1
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• pp.78-87
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• 2004

This paper presents deterministic, worst-case analysis of a queueing system whose multiple homogeneous input streams are regulated by the associated leaky buckets and the queueing system that has a single stream regulated by the jumping-window. Queueing delay averaged over all items is used for performance measure, and the worst-case input traffic and the worst-case performance are identified for both queueing systems. For the former queueing system, the analysis explores different phase relations among leaky-bucket token generations. This paper observes how the phase differences among the leaky buckets affect the worst-case queueing performance. Then, this paper relates the worst-case performance of the former queueing system with that of the latter (the single stream case, as in the aggregate streams from many users, whose item arrivals are regulated by one jumping-window). It is shown that the worst-case performance of the latter is identical to that of the former in which all leaky buckets have the same phase and have particular leaky bucket parameters.

• Aerospace Engineering and Technology
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• v.7 no.2
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• pp.58-66
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• 2008

In the space environment, many other things to design electronic circuits should be considered with respect to commercial circuit design. The first thing is that electronics in space are likely to be exposed to radiation effects and the second thing is that it is impossible to repair or replace electronic parts after once spacecraft was launched. In this severe situation, very strict and tight worst case analysis conditions should be applied to the electronics in space environment to do its own function well without any problems during the overall mission period. So this paper summarizes worst case input conditions and methods which are specified in the ESA Worst Case Analysis Specification (ECSS-Q-30-01A) and proposes the results of Worst Case Analysis for one simple electronic circuit which is implemented at a real On-Board Computer in the Low Earth Orbit Satellite.

• Journal of Computing Science and Engineering
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• v.5 no.2
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• pp.131-140
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• 2011

Different cores typically share the last-level cache in a multi-core processor. Threads running on different cores may interfere with each other. Therefore, the multi-core worst-case execution time (WCET) analyzer must be able to safely and accurately estimate the worst-case inter-thread cache interference. This is not supported by current WCET analysis techniques that manly focus on single thread analysis. This paper presents a novel approach to analyze the worst-case cache interference and bounding the WCET for threads running on multi-core processors with shared L2 instruction caches. We propose to use an interference matrix to model inter-thread interference, on which basis we can calculate the worst-case inter-thread cache interference. Our experiments indicate that the proposed approach can give a worst-case bound less than 1%, as in benchmark fib-call, and an average 16.4% overestimate for threads running on a dual-core processor with shared-L2 cache. Our approach dramatically improves the accuracy of WCET overestimatation by on average 20.0% compared to work.

• Aerospace Engineering and Technology
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• v.8 no.1
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• pp.162-171
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• 2009

Linear regulator for generating various voltages in satellite electronics is implemented with radiation harden regulator chips or simple linear regulator circuits. For implementing linear regulator circuits, the detail design can be various. But the worst case analysis method and interesting analysis items for the linear regulator circuits can be generalized. So this paper describes and summarizes the general worst case analysis method and interesting analysis items for the conventional linear regulator circuits.

• Journal of Computing Science and Engineering
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• v.5 no.1
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• pp.1-18
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• 2011

As the first step toward real-time multi-core computing, this paper presents a novel approach to bounding the worst-case performance for threads running on multi-core processors with shared L2 instruction caches. The idea of our approach is to compute the worst-case instruction access interferences between different threads based on the program control flow information of each thread, which can be statically analyzed. Our experiments indicate that the proposed approach can reasonably estimate the worst-case shared L2 instruction cache misses by considering the inter-thread instruction conflicts. Also, the worst-case execution time (WCET) of applications running on multi-core processors estimated by our approach is much better than the estimation by simply assuming all L2 instruction accesses are misses.

• Journal of the Korean Society of Industry Convergence
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• v.20 no.3
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• pp.205-212
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• 2017

This paper focuses on worst-case delay analysis of the time-triggered IEEE 802.15.4 protocol to satisfy the industrial quality-of-service (QoS) performance. The IEEE 802.15.4 protocol is considered to be unsuitable for industrial networks because its medium access control method is contention-based CSMA/CA, which exhibits unstable performance with an unbounded delay distribution under heavy traffic. To avoid these limitations, this paper presents a time-triggered version of the nonbeacon-enabled network of IEEE 802.15.4 that relies on a time division multiplexing access (TDMA) method implemented in the application layer without any modification of specification. The timing analysis of this time-triggered IEEE 802.15.4 was executed, and the worst-case transmission delay was calculated. Based on this analysis, the time-triggered IEEE 802.15.4 is a promising alternative for wireless industrial networking.

• Transactions of the Korean Society of Automotive Engineers
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• v.10 no.5
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• pp.114-120
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• 2002

In a distributed real-time control system, it is essential to confirm the timing behavior of all tasks because these tasks of each real-time controller have to finish their processes within the specified time intervals called a deadline. In order to satisfy this objective, the timing analysis of a distributed real-time system such as shcedulability test must be performed during the system design phase. In this study, a simple application of CAN fur a vehicle body network system is formulated to apply to a holistic scheduling analysis, and the worst-case execution time (WCET) and the worst-case end-to-end response time (WCRT) are evaluated in the point of holistic system view.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.6
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• pp.637-646
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• 1988

The CMOS physical parameters are extracted using by processing models in fabrication steps, processing parameters, fabrication disturbances, control parameters. Statistical CMOS process and device simulator is proposed to evaluate the effect of inherent fluctuations in IC fabrication. Using this simulator, we perform worst case analysis in terms of statistically independent disturbances and compare this proposed method to Monte Carlo method, previous Worst Case method. And simulation results with this proposed method are more accurate than the past worst case analysis. This package is written in C language and runs on a IBM PC AT(OPUS).

• Transactions of the Korean Society of Mechanical Engineers
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• v.13 no.3
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• pp.554-560
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• 1989

An optimal design technique is used as a systematic approach to analyze the worst case of a circulating type ropeway for a given geometry and operating conditions. Worst case is meant here the case when the positions and weights of the cars are so conditioned that the minimum of all the reaction forces between the main rope and the towers is minimum. In the course of this study, a general theory for the deflections and tensions of the main rope were also derived taking into account of the variation of the weights and positions of the individual cars. And through an analysis of example ropeways, some general conditions for the worst case are deduced.