• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.1
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• pp.618-624
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• 2017

In Seoul and most metropolitan cities, urban trains are delayed due to high congestion during commute times. The delay effect of passengers boarding and disembarking is also significant. In this study, a wide passenger door system was developed as a way to improve the scheduled speed of urban trains by decreasing the passengers' flow time. The door size was defined experimentally to shorten the entrance time. The optimum door size was also determined to improve the stop precision performance of the train while considering the interference effect with peripheral devices. Because the change in door size changes the structural characteristics of the vehicle, the structural stability of a train was analyzed numerically. A prototype of the wide door system was made, and the proposed design was verified using functional and endurance tests. The systematic development process can be used as design data for door size definition and system production when applying a wide door to improve the scheduled speed.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.7
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• pp.740-748
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• 2016

IT and communication technologies has contributed significantly to the convenience of passengers and the financial management of stations in accordance with the task automation in the field of the urban railway system. The foundation of the above development is based on the large amounts of data from various sensors installed in railways, trains, and stations. In particular, the sensor network that is installed in the station and train has played an important role in the railway information system. The performance of AP is affected by the number of APs and their locations installed in the station. In the installation of APs in stations, the intensity of the radio wave of the AP on its underlying position is considered to determine the number and position of APs. This paper proposes a method to estimate the number of APs and their position based on the structure of the underlying station and implemented a simulator to simulate the performance of the proposed method. The implemented simulator was applied to the decision of AP installation at Busan Seomyeon station to evaluate its performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37B no.9
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• pp.778-786
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• 2012

Sensors that are used on wireless sensor networks can be divided into two types: directional sensors, such as PIR, image, and electromagnetic sensors; and non-directional sensors, such as seismic, acoustic and magnetic sensors. In order to guarantee the line-of-sight of a directional sensor, the installation location of the sensor must be higher than ground level. Among non-directional sensors, seismic sensors should be installed on the ground in order to ensure the maximal performance. As a result, seismic sensors may have network connectivity problems due to communication failure. In this paper, we propose a 3D node deployment method to maximize the coverage and the network connectivity considering the sensor-specific properties. The proposed method is for non-directional sensors to be placed on the ground, while the directional sensor is installed above the ground, using trees or poles, to maximize the coverage. As a result, through the topology that the detection data from non-directional sensors are transmitted to the directional sensor, we can maximize the network connectivity. Simulation results show that our strategy improves sensor coverage and network connectivity.

• Journal of Digital Convergence
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• v.11 no.4
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• pp.221-227
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• 2013

RFID is an automatic identification technology that can control a range of information via IC chips and radio communication. Also known as electronic tags, smart tags or electronic labels, RFID technology enables embedding the overall process from production to sales in an ultra-small IC chip and tracking down such information using radio frequencies. Currently, RFID-based application and development is in progress in such fields as health care, national defense, logistics and security. RFID structure consists of a reader that reads tag information, a tag that provides information and the database that manages data. Yet, the wireless section between the reader and the tag is vulnerable to security issues. To sort out the vulnerability, studies on security protocols have been conducted actively. However, due to difficulties in implementation, most suggestions are concerned with theorem proving, which is prone to vulnerability found by other investigators later on, ending up in many troubles with applicability in practice. To experimentally test the security of the protocol proposed here, the formal verification tool, CasperFDR was used. To sum up, the proposed protocol was found to be secure against diverse attacks. That is, the proposed protocol meets the safety standard against new types of attacks and ensures security when applied to real tags in the future.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.465-469
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• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer (PADFE) using a 0.25-${\mu}{\textrm}{m}$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stage are inserted into the critical path of the ADFE by using delayed least-mean-square (DLMS) algorithm Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The singl-chip PADFE contains about 205,000 transistors on an area of about 1.96$\times$1.35-$\textrm{mm}^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.12
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• pp.831-841
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• 2014

The attacker can access the RFID systems illegally because authentication operation on the RFID systems are performed in wireless communication. Authentication methods based on the PUF were presented to defend attacks. Because of Hash and AES, the cost is expensive for the low-cost RFID tag. In this paper, the PUF-based encryption processor and the mutual authentication protocol are proposed for low-cost RFID authentication. The challenge-response pairs (PUF's input and output) are utilized as the authentication key and encrypted by the PUF's characteristics. The encryption method is changed each session and XOR operation with random number is utilized. Therefore, it is difficult for the attacker to analyze challenge-response pairs and attack the systems. In addition, the proposed method with PUF is strong against physical attacks. And the method protects the tag cloning attack by physical attacks because there is no authentication data in the tag. Proposed processor is implemented at low cost with small footprint and low power.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.2
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• pp.9-17
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• 2010

Recently, there has been much interest in orthogonal frequency division multiplexing (OFDM) for next generation wireless wideband communication systems. OFDM is a special case of multicarrier transmission, where a single data stream is transmitted over a number of lower-rate subcarriers. One of the main reasons to use OFDM is to increase robustness against frequency-selective fading or narrowband interference. However, in the radio systems it is also important to distortion introduced by high power amplifiers (HPA's) such as solid state power amplifier (SSPA) considered in this paper. Since the signal amplitude of the OFDM system is Rayleigh-distributed, the performance of the OFDM system is significantly degraded by the nonlinearity of the HPA in the OFDM transmitter. In this paper, we propose a canonical piecewise-linear (PWL) model based digital predistorter to prevent signal distortion and spectral re-growth due to the high peak-to-average power ratio (PAPR) of OFDM signal and the nonlinearity of HPA's. Computer simulation on an OFDM system under additive white Gaussian noise (AWGN) channels with QPSK, 16-QAM and 64-QAM modulation schemes and modulator/demodulator implemented with 1024-point FFT/IFFT, demonstrate that the proposed predistorter achieves significant performance improvement by effectively compensating for the nonlinearity introduced by the SSPA.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.48 no.6
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• pp.63-70
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• 2011

A bicycle is different from vehicles in the structure that a rider is fully exposed to the surrounding environment. Therefore, it needs to make use of prior information about local weather, air quality, trail road condition. Moreover, since it depends on human power for moving, it should acquire route property such as hill slope, winding, and road surface to improve its efficiency in everyday use. Recent mobile applications which are to be used during bicycle riding let us aware of the necessity of development of intelligent bicycles. This study aims to develop a riding state (up-hill, down-hill, accelerating, braking) recognition algorithm using a low-power wrist watch type embedded system which has 3-axis accelerometer and wireless communication capability. The developed algorithm was applied to 19 experimental riding data and showed more than 95% of correct recognition over 83.3% of the total dataset. The altitude and temperature sensor also in the embedded system mounted on the bicycle is being used to improve the accuracy of the algorithm. The developed riding state recognition algorithm is expected to be a platform technology for intelligent bicycle interface system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.97-103
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• 2004

In this paper, we propose a high speed block turbo code decoding algorithm and an efficient hardware architecture. The multimedia wireless data communication systems need channel codes which have the high-performance error correcting capabilities. Block turbo codes support variable code rates and packet sizes, and show a high performance due to a soft decision iteration decoding of turbo codes. However, block turbo codes have a long decoding time because of the iteration decoding and a complicated extrinsic information operation. The proposed algorithm using the threshold that represents a channel information reduces the long decoding time. After the threshold is decided by a simulation result, the proposed algorithm eliminates the calculation for the bits which have a good channel information and assigns a high reliability value to the bits. The threshold is decided by the absolute mean and the standard deviation of a LLR(Log Likelihood Ratio) in consideration that the LLR distribution is a gaussian one. Also, the proposed algorithm assigns '1', the highest reliable value, to those bits. The hardware design result using verilog HDL reduces a decoding time about 30% in comparison with conventional algorithm, and includes about 20K logic gate and 32Kbit memory sizes.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.59-67
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• 2016

With the enhancement of built-in communication capabilities in various meters and wearable devices, which implies Internet of things (IoT), the demand of small-area embedded processors has increased. In this paper, we introduce a small-area 32-bit pipelined processor, Juno, which is available in the field of IoT. Juno is an EISC (Extendable Instruction Set Computer) machine and has a 2/3-stage pipeline structure to reduce the data dependency of the pipeline. It has a simple pipeline controller which only controls the program counter (PC) and two pipeline registers. It offers $32{\times}32=64$ multiplication, 64/32=32 division, $32{\times}32+64=64$ MAC (multiply and accumulate) operations together with 32*32=64 Galois field multiplication operation for encryption processing in wireless communications. It provides selective inclusion of these algebraic logic blocks if necessary in order to reduce the area of the overall processor. In this case, the gate count of our integer core amounts to 12k~22k and has a performance of 0.57 DMIPS/MHz and 1.024 Coremark/MHz.