• Title/Summary/Keyword: wireless SoC

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Design of Miniaturized Wireless Sensor Node Using System-on-Chip (SoC를 이용한 소형 무선 센서 노드 설계)

  • Kim, Hyun-Joong;Yang, Hyun-Ho
    • Proceedings of the KAIS Fall Conference
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    • 2009.12a
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    • pp.190-193
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    • 2009
  • The most essential element in wireless sensor network is wireless sensor node which collects environmental information and transmits it to the user application systems. Recently, due to the technological advancement, wireless sensor nodes are become smaller, more intelligent and less power consuming. Especially, SoC(System-on-Chip) technology, which unifies the MCU, RF module, memory and other element inside one chip, plays an important part for miniaturization of sensor node, hence reduces the manufacturing expenses. In this paper, we have designed a miniaturized wireless sensor node for wireless sensor network using commercial SoC technology and discussed about some application scenario and additional considerations.

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Design and Implementation of Magnetic Induction based Wireless Underground Communication System Supporting Distance Measurement

  • Kim, Min-Joon;Chae, Sung-Hun;Shim, Young-Bo;Lee, Dong-Hyun;Kim, Myung-Jin;Moon, Yeon-Kug;Kwon, Kon-Woo
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.13 no.8
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    • pp.4227-4240
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    • 2019
  • In this paper, we present our proposed magnetic induction based wireless communication system. The proposed system is designed to perform communication as well as distance measurement in underground environments. In order to improve the communication quality, we propose and implement the adaptive channel compensation technique. Based on the fact that the channel may be fast time-varying, we keep track of the channel status each time the data is received and accordingly compensate the channel coefficient for any change in the channel status. By using the proposed compensation technique, the developed platform can reliably communicate over distances of 10m while the packet error rate is being maintained under 5%. We also implement the distance measurement block that is useful for various applications that should promptly estimate the location of nearby nodes in communication. The distance between two nodes in communication is estimated by generating a table describing pairs of the magnetic signal strength and the corresponding distance. The experiment result shows that the platform can estimate the distance of a node located within 10m range with the measurement error less than 50cm.

Design of 868/915MHz SoC System Architecture for Wireless Personal Area Network (개인 무선 통신을 위한 868/915MHz SoC 시스템 구조 설계)

  • Park, Joo-Ho;Oh, Jung-Yeol;Ko, Young-Joon;Kil, Min-Su;Kim, Jae-Young
    • IEMEK Journal of Embedded Systems and Applications
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    • v.2 no.1
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    • pp.24-30
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    • 2007
  • According to development of wireless communication technologies, we need not only high data rate but low data rate system of low power consumption. This low data rate system is utilized in the field of home automation, health care, sensoring and monitoring, etc. IEEE 802.15.4 LR-WPAN system is the best choice for realizing ubiquitous networking system. In this paper SoC Architecture for IEEE 802.15.4 Low Rate WPAN is designed. IEEE 802.15.4 Low Rate WPAN system serves the functions and realization of home area network. We propose the SoC architecture for 868/915MHz frequency band of IEEE 802.15.4 Low Rate WPAN system. The key issue is to design SoC architecture which provides the function of Low Rate WPAN system to meet the requirement of IEEE 802.15.4 standards.

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Low Power SoC Modem Design for High-Speed Wireless Communications (초고속 무선 통신을 위한 저전력 모뎀 SoC 설계)

  • Kim, Yong-Sung;Lim, Yong-Seok;Hong, Dae-Ki
    • Journal of the Semiconductor & Display Technology
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    • v.9 no.2
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    • pp.7-10
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    • 2010
  • In this paper, we design a modem SoC (System on Chip) for low power consumption and high speed wireless communications. Among various schemes of high speed communications, an MB-OFDM (Multi Band-Orthogonal Frequency Division Multiplexing) UWB (Ultra-Wide-Band) chip is designed. The MB-OFDM uses wide-band frequency to provide high speed data rate. Additionally, the system imposes no interference to other services. The 90nm CMOS (Complementary Metal-Oxide Semiconductor) technology is used for the SoC design. Especially, power management mode is implemented to reduce the power consumption.

Wireless Communication System for T/C based on DSRC (DSRC 기반의 T/C 무선통신 시스템 개발)

  • 성창우;강대성
    • Journal of Korean Port Research
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    • v.14 no.3
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    • pp.313-319
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    • 2000
  • In this paper, we proposed the model of wireless communication for ACTS using DSRC and the DSRC system for T/C. The proposed wireless communication model is how to join with DSRC and other wireless communication in port. The DSRC system for T/C is the first application to the unit of port Facilities Automation on stacking area. The DSRC system is communicated between OBE and RSE using 5.8Hz ISM band frequency. The previous works of DSRC applications are gate automation. In these cases, the road trackers are difficult to obtain information of the port in the stacking area. So we used the DSRC for the wireless communication for the port Facilities Automation. Using DSRC, the load trackers obtain more information in the port and contacts to ITS on back-roads of port. The proposed communication system is serviced to reelection of port statistics.

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FGPA Design and SoC Implementation for Wireless PAN Applications (무선 PAN 응용을 위한 FPGA 설계 및 SoC)

  • Kim, Young-Sung;Kim, Sun-Hee;Hong, Dae-Ki
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.9 no.2
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    • pp.462-469
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    • 2008
  • In this paper, we design the FPGA (Field-Programmable Gate Array) of the KOINONIA WPAN (Wireless Personal Area Network), and implement the SoC (System on Chip). We use the redundant bits to make a constant-amplitude in a modulator part. Additionally, the SNR (Signal to Noise Ratio) performance of the demodulator is improved by using the redundant bits in decoding steps. The four-million FPGA of the KOINONIA WPAN can be operated at 44MHz frequency. The PER (Packet Error Rate) of the designed FPGA with RF (Radio Frequency) module is below 1% at the -86dB MIPLS (Minimum Input Power Level Sensitivity), and the SNR is about 13dB. The SoC is implemented by using Hynix 0.25um CMOS (Complementary Metal Oxide Semiconductor) process. The size of the SoC is $6.52mm{\times}6.92mm$.

Development of an Embedded Bluetooth Audio Streaming Solution on SoC Platform (SoC 플랫폼 상에서 임베디드 블루투스 오디오 스트리밍 솔루션 개발)

  • Kim, Tae-Hyoun
    • The KIPS Transactions:PartA
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    • v.13A no.7 s.104
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    • pp.589-598
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    • 2006
  • In this paper, we describe the development and optimization of an embedded Biuetooth solution on an SoC platform for real-time audio streaming over a Bluetooth wireless link. The solution includes embedded Bluetooth protocol stack and profile simplemented on a virtual operating system for portability, and other optimization techniques to fully exploit the benefits of multimedia-oriented SoC. The optimization techniques implemented in this paper are memory access minimization by using on-chip scratch pad memory, codec library optimization with DSP and parallel memory access instruction set, and dynamic audio quality adjustment regarding current wireless link status. Experimental results show that the optimized solution presented in this paper can support high-qualify audio streaming without the support of external memory.

Embedded ARM based SoC Implementation for 5.8GHz DSRC Communication Modem (임베디드 ARM 기반의 5.8GHz DSRC 통신모뎀에 대한 SOC 구현)

  • Kwak, Jae-Min;Shin, Dae-Kyo;Lim, Ki-Taek;Choi, Jong-Chan
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.43 no.11 s.353
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    • pp.185-191
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    • 2006
  • DSRC((Dedicated Short Range Communication) is dedicated short range communication for wireless communications between RSE(Road Side Equipment) and OBE(On-Board Unit) within vehicle moving high speed. In this paper, we implemented 5.8GHz DSRC modem according to Korea TTA(Telecommunication Technology Association) standard and investigated implementation results and design process for SoC(System on a Chip) embedding ARM CPU which control overall signal and process arithmetic work. The SoC is implemented by 0.11um design technology and 480pins EPBGA package. In the implemented SoC ($Jaguar^{TM}$), 5.8GHz DSRC PHY(Physical Layer) modem and MAC are designed and included. For CPU core ARM926EJ-S is embedded, and LCD controller, smart card controller, ethernet MAC, and memory controller are designed as main function.

Design of Smart Frame SoC to support the IoT Services (IoT 서비스를 지원하는 Smart Frame SoC 설계)

  • Yang, Dong-hun;Hwang, In-han;Kim, A-ra;Guard, Kanda;Ryoo, Kwang-ki
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2015.10a
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    • pp.503-506
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    • 2015
  • In accordance with IoT(Internet of Things) commercialization, the need to design SoC-based hardware platform with wireless communication is increasing. This paper therefor proposes an SoC platform architecture with Smart Frame System inter-communicating between devices. Wireless communication functions and high-performance real-time image processing hardware structure was applied to existing digital photo frame. We developed a smart phone application to control the smart frame through Bluetooth communication. The SoC platform hardware consists of CIS controller, Memory controller, ISP(Image Signal Processing) module for image scaling, Bluetooth Interface for inter-communicating between devices, VGA/TFT-LCD controller for displaying video. The Smart Frame System to support the IoT services was implemented and verified using HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA. The operating frequency is 54MHz.

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