• 한국전기전자재료학회논문지
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• 제13권2호
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• pp.120-124
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• 2000

In this paper, the effects of trap distribution on switching characteristis of a lateral insulated gate bipolar transistor (LIGBT) are investigated. The simulations are performed in order to to analyze the effect of the positon, width and concentration of trap distribution model with a reduced minority carrier lifetime using 2D device simulator MEDICI. The turn off time for the proposed LIGBT model A with the trap injection is 0.8$mutextrm{s}$. These results indicate the improvement of about 2 times compared with the conventional LIGBT. It is shown that the trap distribution model is very effective to reduce the turn-off time with a little increasing of on-state voltage drop.

• 한국전기전자재료학회논문지
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• 제30권8호
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• pp.491-495
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• 2017

We investigated solution-processed indium-zinc oxide (IZO) thin-film transistors (TFTs) by inserting a 2-(4-biphenylyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole (PBD) buffer layer. This buffer layer efficiently tuned the energy level between the semiconducting oxide channel and metal electrode by increasing charge extraction, thereby enhancing the overall device performance: the IZO TFT with embedded PBD layer (thickness: 5 nm; width: $2,000{\mu}m$; length: $200{\mu}m$) exhibited a field-effect mobility of $1.31cm^2V^{-1}s^{-1}$, threshold voltage of 0.12 V, subthreshold swing of $0.87V\;decade^{-1}$, and on/off current ratio of $9.28{\times}10^5$.

• Transactions on Electrical and Electronic Materials
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• 제12권6호
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• pp.245-248
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• 2011

The scaling down of metal oxide semiconductor field-effect transistors (MOSFETs) for the last several years has contributed to the reduction of the scaling variables and device parameters as well as the operating voltage of the MOSFET. At the same time, the variation in the electrical characteristics of MOSFETs is one of the major issues that need to be solved. Especially because the issue with variation is magnified as the drive voltage is decreased. Therefore, this paper will focus on the variations between electrical characteristics and drain voltage. In order to do this, the test patterned multi-finger MOSFETs using 90-nm process is used to investigate the characteristic variations, such as the threshold voltage, DIBL, subthreshold swing, transconductance and mobility via parasitic resistance extraction method. These characteristics can be analyzed by varying the gate width and length, and the number of fingers. Through this modeling scheme, the characteristic variations of multi-finger MOSFETs can be analyzed.

• Journal of the Korean Physical Society
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• 제73권10호
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• pp.1502-1505
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• 2018

We present a design for hybrid circular Bragg gratings (hCBGs) for efficiently extracting single-photons emitted by InAs quantum dots (QDs) embedded in GaAs. Finite-difference time-domain simulations show that a very high photon collection efficiency (PCE) up to 96% over a 50 nm bandwidth and pronounced Purcell factors up to 19 at cavity resonance are obtained. We also systematically investigate the geometry parameters, including the $SiO_2$ thickness, grating period, gap width and the central disk radius, to improve the device performances. Finally, the PCEs and the Purcell factors of QDs located at different positions of the hCBG are studied, and the results show great robustness against uncertainties in the location of the QD.

• 한국정보통신학회논문지
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• 제24권5호
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• pp.682-685
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• 2020

In this paper, we analyze the dominant noise source of conventional inductively degenerated common-source (CS) cascode low noise amplifier (LNA) when width and gate length of stacked transistors vary. Analytical MOSFET and its noise model are used to estimate the contributions of noise sources. All parameters are based on measured data of 60nm, 90nm and 130nm CMOS devices. Based on the noise analysis for different frequencies and device parameters including process nodes, the dominant noise source can be analyzed to optimize noise figure on the configuration. We verified analytically that the intuctively degenerated CS topology can not sustain its benefits in noise above a certain operation frequency of LNA over different process nodes.

• 한국정보통신학회논문지
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• 제24권5호
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• pp.678-681
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• 2020

In this paper, we analyzed the noise figure of cascode low noise amplifier (LNA) based on the measured data of 65nm CMOS devices. By using the channel thermal noise model of transistors, we expanded noise figure equation and divided the equation into three parts to see its contributions to noise figure. We also varied design parameters such as bias point, transistor gate width, and operating frequency. Our results show that different noise sources dominate at the different operating frequencies. One can easily find the noise transition frequency with device models in ahead of the practical design. Therefore, this research provides a low noise design approach for different operating frequencies.

• 소성∙가공
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• 제33권4호
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• pp.291-300
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• 2024

To compare the lubrication performance improvement of different laser texturing surface treatment patterns, ring-shaped specimens were prepared by processing line and dot patterns using a fiber laser device. Ring compression tests were conducted to compare the reduction rates of the inner diameter corresponding to the same height reduction of the specimens. Laser processing conditions were set to create patterns with a depth of 9㎛ and a width of 45㎛. Ring specimens were processed with varying spacings between dots and lines. The forging lubricant TECTYL FORM CF 351S was uniformly applied to the upper and lower compression tools, and the rings were compressed by 40% using a hydraulic press, after which the inner diameter was measured. The comparison of inner diameter reduction rates indicated that pattern processing improves lubrication performance, with line patterns being more effective than dot patterns in enhancing lubrication performance.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.189-189
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• 2009

This work was focused on the dielectrophoretic force of fullerenes dispersed in liquid crystal host medium, which are investigated in the homogeneously aligned liquid crystal (NLC) cells driven by external electric field. A fullerene of 10 wt% was doped into the LC medium and its electric field induced motion was controlled by both in-plane and vertical electric field. When the electric field was applied, the fullerene start to move in direction of applied electric field. The dark, grey and white states in the proposed device can be obtained by suitable combination of the polarity of applied electric field. The w and l are the width and distance between the electrodes. The reflectance at different l was measured and was found to be increased with increasing l. The dynamical motions of fullerene particles in LC medium suggest that fullerene can be designed for electronic-paper like displays.

• 전자공학회논문지S
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• 제34S권5호
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• pp.15-24
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• 1997

We propose a tunable add/drop filter in a form of an all-fiber mach-zehnder interferometer iwth one bragg grating at each arm. This device can be tuned by inducing a strain in the bragg grating. We also theoretically analyze the outut characteristics of the tunable add/drop filter. As a result of simulation, we know that the proposed tunable add/drop filter works well. When 2*10$^{-3}$ of strain is induced, the reflected spectrum shifts about 3nm. And its reflected spectral width is about 0.3nm. In this case roughly 5 channels can be tuned, assuming the channel spacing is 0.3nm. When the pathlengths of the both arms are not the same, the transmissivities at the add and output ports and the reflectivity at the tap port varies sinusoidally with the pthlength difference. To maintain the transmissivities above 90% in the wavelength tuning range of 20nm the pathlength difference less than 16.mu.m is required.

• 한국세라믹학회지
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• 제54권1호
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• pp.66-69
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• 2017

In this study, the fabrication and electrical properties of aligned single-walled carbon nanotube (SWCNT) networks using a template-based fluidic assembly process are presented. This complementary metal-oxide-semiconductor (CMOS)-friendly process allows the formation of highly aligned lateral nanotube networks on $SiO_2/Si$ substrates, which can be easily integrated onto existing Si-based structures. To measure outstanding electrical properties of organized SWCNT devices, interfacial contact resistance between organized SWCNT devices and Ti/Au electrodes needs to be improved since conventional lithographic cleaning procedures are insufficient for the complete removal of lithographic residues in SWCNT network devices. Using optimized purification steps and controlled developing time, the interfacial contact resistance between SWCNTs and contact electrodes of Ti/Au is reached below 2% of the overall resistance in two-probe SWCNT platform. This structure can withstand current densities ${\sim}10^7A{\cdot}cm^{-2}$, equivalent to copper at similar dimensions. Also failure current density improves with decreasing network width.