• Journal of Communications and Networks
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• v.6 no.2
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• pp.163-172
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• 2004

Ultra Wide Bandwidth (UWB) spread-spectrum techniques will playa key role in short range wireless connectivity supporting high bit rates availability and low power consumption. UWB can be used in the design of wireless local and personal area networks providing advanced integrated multimedia services to nomadic users within hot-spot areas. Thus the assessment of the possible interference caused by UWB devices on already existing narrowband and wideband systems is fundamental to ensure nonconflicting coexistence and, therefore, to guarantee acceptance of UWB technology worldwide. In this paper, we study the coexistence issues between an indoor UWB-based system (hot-spot) and outdoor point to point (PP) links and Fixed Wireless Access (FWA) systems operating in the 3.5 - 5.0 GHz frequency range. We consider a realistic UWB master/slave system architecture and we show through computer simulation, that in all practical cases UWB system can coexist with PP and FWA without causing any dangerous interference.

• Journal of Advanced Navigation Technology
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• v.6 no.2
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• pp.97-103
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• 2002

A recent technology trends in synthetic aperture radar(SAR) requires the ultra high resolution performance in detecting and precisely identifying the targets. In this paper, as a technique for enhancing the radar range resolution, the wide band chirp connection algorithm is presented by stitching the several chirp modules with unit bandwidth based on the linear frequency modulated chirp signal waveform. The principles of the digital chirp signal generation and its architecture for implementation is described with the wide band chirp signal generator, modulator, and demodulator. The performance analysis for the presented algorithm is given with the simulation results.

• Journal of electromagnetic engineering and science
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• v.5 no.1
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• pp.8-13
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• 2005

The InGaP/GaAs hetero-junction bipolar transistor(HBT) monolithic voltage-controlled dielectric resonator oscillator(VCDRO) is first demonstrated for a Ku-band low noise block down-converter(LNB) system. The on-chip voltage control oscillator core employing base-collector(B-C) junction diodes is proposed for simpler frequency tuning and easy fabrication instead of the general off-chip varactor diodes. The fabricated VCDRO achieves a high output power of 6.45 to 5.31 dBm and a wide frequency tuning range of ]65 MHz( 1.53 $\%$) with a low phase noise of below -95dBc/Hz at 100 kHz offset and -115 dBc/Hz at ] MHz offset. A]so, the InGaP/GaAs HBT monolithic DRO with the same topology as the proposed VCDRO is fabricated to verify that the intrinsic low l/f noise of the HBT and the high Q of the DR contribute to the low phase noise performance. The fabricated DRO exhibits an output power of 1.33 dBm, and an extremely low phase noise of -109 dBc/Hz at 100 kHz and -131 dBc/Hz at ] MHz offset from the 10.75 GHz oscillation frequency.

• The Journal of Information Technology
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• v.5 no.4
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• pp.173-183
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• 2002

In this paper, we propose an efficient forecasting methodology of the mid and long-term frequency demand in Korea. The methodology consists of the following three steps: classification of basic service group, calculation of effective traffic, and frequency forecasting. Based on the previous studies, we classify the services into wide area mobile, short range radio, fixed wireless access and digital video broadcasting in the step of the classification of basic service group. For the calculation of effective traffic, we use the measures of erlang and bps. The step of the calculation of effective traffic classifies the user and basic application, and evaluates the effective traffic. Finally, in the step of frequency forecasting, different methodology will be proposed for each service group.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.3
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• pp.34-41
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• 2011

This paper presents a wide tuning range, fine-resolution DCO (Digitally Controlled Oscillator) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. To cover the wide tuning range, an automatic three-step coarse tuning scheme is proposed. The DCO total frequency tuning range is 1.4 GHz (2.1 GHz to 3.5 GHz), it is 58 % at 2.4 GHz. An effective frequency resolution is 0.14 kHz/LSB. The proposed DCO is implemented in 0.13 ${\mu}m$ CMOS process. The total power consumption is 6.6 mW from a 1.2 V supply voltage. The phase noise of the DCO output at 2.4 GHz is -120.67 dBc/Hz at 1 MHz offset.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.32-38
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• 2011

This paper describes implementation of the 5.0GHz RF frequency synthesizer with 0.18${\mu}m$ silicon CMOS technology being used as an application of the IEEE802.15.4 USN sensor node transceiver modules. To get good performance of speed and noise, design of the each module like VCO, prescaler, 1/N divider, fractional divider with ${\Sigma}-{\Delta}$ modulator, and common circuits of the PLL has been optimized. Especially to get excellent performance of high speed and wide tuning range, N-P MOS core structure and 12 step cap banks have been used in design of the VCO. The chip area including pads for testing is $1.1{\times}0.7mm^2$, and the chip area only core for IP in SoC is $1.0{\times}0.4mm^2$. Through analysing of the fabricated frequency synthesizer, we can see that it has wide operation range and excellent frequency characteristics.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2004.11a
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• pp.763-766
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• 2004

Recently, various acoustic artifacts that contains speaker have been produced such as cellular phone. Speaker consists of diaphragm generating sound and coil vibrating diaphragm. Generally, good speaker means that it has a wide frequency range, high output power rate to input power and flat sound pressure level in specified frequency range. Acoustic characteristic was estimated through the experiment and computer simulation, or sound power was controlled with acoustic sensitivity in a natural frequency range fer last decade. However, the flatness of sound pressure level has not been considered to enhance the sound quality of a speaker. Tn this study, a method for speaker design is proposed for a good acoustic characteristic, which is flatness of SPL(sound pressure level) and wideness between the first and second natural frequency. SYSNOISE is used fer acoustic analysis and ANSYS is used for harmonic response analysis and modal analysis. Optimization for acoustic characteristics of a speaker diaphragm is performed using ModelCenter. All analyses are done within a frequency domain. And we confirm that the experimental and computational simulations have similar trend.

• ETRI Journal
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• v.35 no.5
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• pp.797-807
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• 2013

In this paper, an input receiver with a hysteresis characteristic that can work at voltage levels between 0.9 V and 5 V is proposed. The input receiver can be used as a wide voltage range Schmitt trigger also. At the same time, reliable circuit operation is ensured. According to the research findings, this is the first time a wide voltage range Schmitt trigger is being reported. The proposed circuit is compared with previously reported input receivers, and it is shown that the circuit has better noise immunity. The proposed input receiver ends the need for a separate Schmitt trigger and input buffer. The frequency of operation is also higher than that of the previously reported receiver. The circuit is simulated using HSPICE at 0.35-${\mu}m$ standard thin oxide technology. Monte Carlo analysis is conducted at different process conditions, showing that the proposed circuit works well for different process conditions at different voltage levels of operation. A noise impulse of ($V_{CC}/2$) magnitude is added to the input voltage to show that the receiver receives the correct logic level even in the presence of noise. Here, $V_{CC}$ is the fixed voltage supply of 3.3 V.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.3
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• pp.158-162
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• 2015

A low phase noise CMOS voltage controlled oscillator(VCO) for multi-band/multi-standard RF Transceivers is presented. For both wide tunability and low phase noise characteristics, Hybrid inductor which uses both bondwire inductor and planar spiral inductor in the same area, is proposed. This approach reduces inductance variation and presents high quality factor without custom-designed single-turn inductor occupying large area, which improves phase noise and tuning range characteristics without additional area loss. An LC VCO is designed in a 0.13um CMOS technology to demonstrate the hybrid inductor concept. The measured phase noise is -121dBc/Hz at 400KHz offset and -142dBc/Hz at 3MHz offset from a 900MHz carrier frequency after divider. The tuning range of about 28%(3.15 to 4.18GHz) is measured. The VCO consumes 7.5mA from 1.3V supply and meets the requirements for GSM/EDGE and WCDMA standard.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.520-527
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• 2016

A new dual-loop digital delay-locked loop (DLL) using a hybrid (binary + sequential) search algorithm is presented to achieve both wide-range operation and high delay resolution. A new phase-interpolation range selector (PIRS) and a variable successive approximation register (VSAR) algorithm are adopted to resolve the boundary switching and harmonic locking problems of conventional digital DLLs. The proposed digital DLL, implemented in a $0.18-{\mu}m$ CMOS process, occupies an active area of $0.19mm^2$ and operates over a wide frequency range of 0.15-1.5 GHz. The DLL dissipates a power of 11.3 mW from a 1.8 V supply at 1 GHz. The measured peak-to-peak output clock jitter is 24 ps (effective pk-pk jitter = 16.5 ps) with an input clock jitter of 7.5 ps at 1.5 GHz. The delay resolution is only 2.2 ps.