• 한국전기전자재료학회논문지
• /
• 제16권5호
• /
• pp.365-371
• /
• 2003

We prepared silicon on insulator(SOI) wafer pairs of Si/1800${\AA}$ -SiO$_2$ ∥ 1800${\AA}$ -SiO$_2$/Si using water direct bonding method. Wafer pairs bonded at room-temperature were annealed by a normal furnace system or a fast linear annealing(FLA) equipment, and the micro-structure of bonding interfaces for each annealing method was investigated. Upper wafer of bonded pairs was polished to be 50 $\mu\textrm{m}$ by chemical mechanical polishing(CMP) process to confirm the real application. Defects and bonding area of bonded water pairs were observed by optical images. Electrical and mechanical properties were characterized by measuring leakage current for sweeping to 120 V, and by observing the change of wafer curvature with annealing process, respectively. FLA process was superior to normal furnace process in aspects of bonding area, I-V property, and stress generation.

• 전자공학회논문지A
• /
• 제32A권3호
• /
• pp.134-142
• /
• 1995

We discovered that each distinct shape of the roof-shaped peaks of (111) facets, which are generated on (110) cross-section of the directly bonded (100) silicon wafer pairs after KOH etching, can be mapped to one of three conditions of the interfacial oxide existing at the bonding interface as follows. That is, thick solid line can be mapped to stabilization, thin solid line to disintegration, and thin broken line to spheroidization. also we confirmed that most of the interfacial oxides of a well-aligned wafer pairs were disintegrated and spheroidized through high-temperature annealing process above 900$^{\circ}$C while the oxide was stabilized persistently when two wafers are bonded rotationally around their common axis perpendicular to the wafer planes.

• 한국재료학회지
• /
• 제12권10호
• /
• pp.820-824
• /
• 2002

It is of importance to know that the bonding strength and interfacial stress of SOI wafer pairs to meet with mechanical and thermal stresses during process. We fabricated Si/2000$\AA$-SiO$_2$ ∥ 2000$\AA$-SiO$_2$/Si SOI wafer pairs with electric furnace annealing, rapid thermal annealing (RTA), and fast linear annealing (FLA), respectively, by varying the annealing temperatures at a given annealing process. Bonding strength and interfacial stress were measured by a razor blade crack opening method and a laser curvature characterization method, respectively. All the annealing process induced the tensile thermal stresses. Electrical furnace annealing achieved the maximum bonding strength at $1000^{\circ}C$-2 hr anneal, while it produced constant thermal tensile stress by $1000^{\circ}C$. RTA showed very small bonding strength due to premating failure during annealing. FLA showed enough bonding strength at $500^{\circ}C$, however large thermal tensile stress were induced. We confirmed that premated wafer pairs should have appropriate compressive interfacial stress to compensate the thermal tensile stress during a given annealing process.

• 한국전기전자재료학회논문지
• /
• 제16권10호
• /
• pp.859-864
• /
• 2003

We prepared SOI(silicon-on-insulator) wafer pairs of Si II SiO$_2$/Si$_3$N$_4$ II Si using wafer direct bonding with an electric furnace annealing(EFA), a fast linear annealing(FLA), and a rapid thermal annealing(RTA), respectively, by varying the annealing temperatures at a given annealing process. We measured the bonding area and the bonding strength with processes. EFA and FLA showed almost identical bonding area and theoretical bonding strength at the elevated temperature. RTA was not bonded at all due to warpage, We report that FLA process was superior to other annealing processes in aspects of surface temperature, annealing time, and bonding strength.

• 한국재료학회지
• /
• 제14권5호
• /
• pp.315-321
• /
• 2004

The void evolution in direct bonding process of $Si/Si_3$$N_4$ ∥ $SiO_2$/Si silicon wafer pairs has been investigated with an infrared camera. The voids that formed in the premating process grew in the conventional furnace annealing process at a temperature of $600^{\circ}C$. The voids are never shrunken even with the additional annealing process at the higher temperatures. We observed that the voids became smaller and disappeared with sequential scanning by our newly proposed fast linear annealing(FLA). FLA irradiates the focused line-shape halogen light on the surface while wafer moves from one edge to the other. We also propose the void shrinking mechanism in FLA with the finite differential method (FDM). Our results imply that we may eliminate the voids and enhance the yield for the direct bonding of wafer pairs by employing FLA.

• 한국재료학회지
• /
• 제12권2호
• /
• pp.117-120
• /
• 2002

We investigated the possibility of direct bonding of the Si ∥SiO$_2$/Si$_3$N$_4$∥Si wafers for Oxide-Nitride-Oxide(ONO) gate oxide applications. 10cm-diameter 2000$\AA$-thick thermal oxide/Si(100) and 500$\AA$-Si$_3$N$_4$LPCVD/Si (100) wafers were prepared, and wet cleaned to activate the surface as hydrophilic and hydrophobic states, respectively. Cleaned wafers were premated wish facing the mirror planes by a specially designed aligner in class-100 clean room immediately. Premated wafer pairs were annealed by an electric furnace at the temperatures of 400, 600, 800, 1000, and 120$0^{\circ}C$ for 2hours, respectively. Direct bonded wafer pairs were characterized the bond area with a infrared(IR) analyzer, and measured the bonding interface energy by a razor blade crack opening method. We confirmed that the bond interface energy became 2,344mJ/$\m^2$ when annealing temperature reached 100$0^{\circ}C$, which were comparable with the interface energy of homeogenous wafer pairs of Si/Si.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1993년도 하계학술대회 논문집 B
• /
• pp.1057-1059
• /
• 1993

Some interested phenomena, which were appeared near the bonding interface, were investigated by angle lapping and delineation method, SEM, and TEM observations. Voids, defects, material continuity, and interfacial oxide stability were observed and discussed in the fusion-bonded Bi-Si or Si-$SiO_2$/Si wafer pairs.

• 한국재료학회지
• /
• 제12권6호
• /
• pp.508-512
• /
• 2002

$2000{\AA}-SiO_2/Si(100)$ and $560{\AA}-Si_3N_4/Si(100)$ wafers, which are 10 cm in diameter, were directly bonded using a rapid thermal annealing method. We fixed the anneal time of 30 second and varied the anneal temperatures from 600 to $1200^{\circ}C$. The bond strength of bonded wafer pairs at given anneal temperature were evaluated by a razor blade crack opening method and a four-point bonding method, respectively. The results clearly slow that the four-point bending method is more suitable for evaluating the small bond strength of 80~430 mJ/$\m^2$ compared to the razor blade crack opening method, which shows no anneal temperature dependence in small bond strength.

• 한국재료학회지
• /
• 제11권7호
• /
• pp.556-561
• /
• 2001

실리사이드반웅을 이용하여 니켈모노실리사이드의 양측계면에 단결정실리콘을 적층시켜 전도성이 우수하며 식각특성이 달라 MEMS용 기판으로 채용이 가능한 SOS (Silicon-on-Silicide) 기판을 제작하였다. 실리콘 기판 전면에 Ni를 열증착법으로$ 1000\AA$두께로 성막하고, 실리콘 기판 경면과 맞블여 후 $300~900^{\circ}C$온도범위에서 15시간동안 실리사이드 처리하여 니켈모노실리사이드가 접합매체로 되는 기판쌍들을 완성하였다. 완성된 기판쌍들은 IR (infrared) 카메라를 이용하여 비파괴적으로 접합상태를 확인하고. 주사전자현미경 (scaning electron microscope)과 투과전자현미경 (tranmission electron microscope)을 이용하여 수직단면 미세구조를 확인하였다. Ni 실리사이드의 상변화가 일어나는 온도를 제외하고는 Si NiSi ∥Si 기판쌍은 기판전면에 52%이상 완전접합이 진행되었음을 확인하였고 생성 실리사이드의 두께에 따라 나타나는 명암부에 비추어 기판쌍 중앙부에 두꺼운 니켈노실리아드가 형성되었다고 판단되었다. 완성된 Si NiSi ∥ Si 기판쌍을 SBM 수직단면에 의괘 확인한 결과 접합이 완성된 기판중심부의 접합계면은 $1000\AA$ 두께의 NiSi가 균일하게 형성되었으며 배율 30,000배의 해상도에서 계면간 분리부분없이 완전한 접합이 진행되었음을 확인하였다. 반면 기판쌍 에지 (edge)부분에는 실리사이드가 헝성되지 않은 비접합상태가 발견되었다. 수직단면루과전자현미경 결과물에 근거하여 접합된 중심부에서는 피접합되는 실리콘의 경면과 니켈이 성막된 실리콘 경면 상부계면에 10-20$\AA$의 비정질막이 발견되었으며, 산화막으로 추정되는 이 막이 접합률을 현저히 저하시키는 것을 확인하였다. 접합이 진행되지 않은 에지부는 이러한 산화막이 열처리 진행중 급격히 성장하여 피접합 실리콘층의 분리가 발생하였다. 따라서 Si NiSi ∥Si 기판쌍의 접합률을 향상시키기 위해서는 피접합 실리콘 계면과 Ni 상부층간의 비정질부를 적극적으로 제거하여야 함을 알 수 있었다.

• 한국재료학회:학술대회논문집
• /
• 한국재료학회 2002년도 춘계 학술발표강연 및 논문개요집
• /
• pp.121-121
• /
• 2002