• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.293-298
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• 2006

Thermopiezoelectric method, using poly silicon heater and a piezoelectric sensor, was proposed for writing and reading in a probe based data storage system. Resistively heated tip writes data bits while scanning over a polymer media and piezoelectric sensor reads data bits from the self-generated charges induced by the deflection of the cantilever. 34${\times}$34 array of thermopiezoelectric nitride cantilevers were fabricated by a single step wafer level transfer method. We analyzed the noise level of the charge amplifier and measured the noise signal. With the sensor and the charge amplifier 20mn of deflection could be detected at a frequency of 10KHz. Reading signal was obtained from the cantilever array and the sensitivity was calculated.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.9
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• pp.834-843
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• 2016

In this paper, the design of a PIN diode S-band transfer-type SP4T including its driver circuit is presented. Each path of the SP4T is composed of the cascade connection of series-shunt PIN diodes to improve the isolation performance. The SP4T is implemented using chip type PIN diodes and a 20 mil AIN substrate fabricated using thin film technology. The driver circuit for the SP4T is designed using a multiplexer and four NMOS-PMOS push-pull pair. From on-wafer measurement, the fabriacted SP4T shows a maximum insertion loss of 1.1 dB and a minimum isolation of 41 dB. The time performance of the driver circuit is evaluated using the packaged PIN diodes with the identical PIN diode chip, and the transition time for on-off and off-on are below 100 nsec. For an input power level of 150 W, the measured insertion loss and isolation are close to those of the on-wafer measurement taking into consideration of the coaxial package mismatch and insertion loss.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.13-13
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• 2009

We have investigated the fabrication and properties of bendable PZT film formed on plastic substrates for the application in flexible memory. These devices used the PZT active layer formed on $SiO_2/Si$ wafer by sol-gel method with optimized device layouts and Pt electrodes. After etching Pt/PZT/Pt layers, patterned by photolithography process. these layers were transferred on PET plastic substrate using elastomeric stamp. The level of performance that can be achieved approaches that of traditional PZT. devices on rigid bulk wafers.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07b
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• pp.811-813
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• 2003

We investigated the electrical properties of self-assembled (4,4'-Di(ethynylphenyl)-2'-nitro-1-thioacetylbenzene), which has been well known as a conducting molecule having possible application to molecular level negative differential resistance(NDR)[1]. Generally, the phenomenon of NDR can be characterized by the decreasing current with the increasing voltage[2]. To deposit the SAM layer onto gold electrode, we transfer the prefabricated nanopores into a 1mM self-assembly molecules in THF solution. Au(111) substrates were prepared by ion beam sputtering method of gold onto the silicon wafer. As a result, we measured the voltage-current properties and confirmed the negative differential resistance properties of self-assembled organic thin film and measured, using Scanning Tunneling Microscopy(STM).

• Journal of the Semiconductor & Display Technology
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• v.4 no.3 s.12
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• pp.29-33
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• 2005

As the integrated devices become more and more sophistcated, the diameter of wafers increased up to 300 mm and strict level of cleaning is necessary to remove the particulates on the surface of wafer. Therefore we need a new type of wet-station which can reduce DI water and chemical in the cleaning process. Moreover, it is important to control the temperature and the concentration of chemical in the wet-station. In the conventional chemical supply system, it is difficult not only to fit the mixing rate of chemicals in cleaning process, but also to fit the quantity and temperature. Thus, we propose a new chemicals supply system, which overcomes above problems by the analysis of fluid and thermal transfer on chemical supply system.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.