• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.1092-1095
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• 2001

Steady state thermal analysis has been done by a finite element method in a diode of 12kV blocking voltage. The diode was fabricated by soldering ten pieces of 1200V diodes in series, capping a dummy wafer at the far end of diode series, and finally wire bonded for building anode and cathode terminal. In order to achieve high voltage and reliability, the edge of each diode was beveled and passivated by resin with a thickness of 25${\mu}$m. It was assumed that the generated heat which is mainly by the on-state voltage drop, 9V for 12kV diode, is dissipated by way of the conduction through diodes layers to bonding wire and of the convection at the surface of passivating resin. It was predicted by the thermal analysis that the temperature rise of a pn junction of the 12kV diode can reach at the range of 16∼34$^{\circ}C$ under the given boundary conditions. The thickness and thermal conductivity(0.3∼3W/m-K) of the passivating resin did little effect to lower thermal resistance of the diode. As the length of the bonding wire increased, which means the distance of heat conduction path became longer, the thermal resistance increased considerably. The thermal analysis results imply that the generated heat of the diode is dissipated mainly by the conduction through the route of diode-dummy wafer-bonding wire, which suggests to minimize the length of the wire for the lowest thermal resistance.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.350-353
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• 2002

High voltage SiC Schottky barrier diodes with field plate structure have been fabricated and characterized. N-type 4H-SiC wafer with an epilayer of ∼10$\^$15/㎤ doping level was used as a starting material. Various Schottky metals such as Ni, Pt, Ta, Ti were sputtered and thermally-evaporated on the low-doped epilayer. Ohmic contact was formed at the backside of the SiC wafer by annealing at 950$^{\circ}C$ for 90 sec in argon using rapid thermal annealer. Field oxide of 550${\AA}$ in thickness was formed by a wet oxidation process at l150$^{\circ}C$ for 3h and subsequently heat-treated at l150$^{\circ}C$ for 30 min in argon for improving oxide quality. The turn-on voltages of the Ni/4H-SiC Schottky diode was 1.6V which was much higher than those of Pt(1.0V), Ta(0.7V) and Ti(0.7). The voltage drop was measured at the current density of 100A/$\textrm{cm}^2$ showing 2.1V for Ni Schottky diode, 1.45V for Pt 1.35V, for Ta, and 1.25V for Ti, respectively. The maximum reverse breakdown voltage was measured 1100V in the file plated Schottky diodes with 101an thick epilayer.

• 한국광학회지
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• 제15권1호
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• pp.79-85
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• 2004

후면의 석영면에 위상 패턴을 형성하여 투과율 조절을 구현한 포토마스크에 대해 보고한다. 위상 패턴의 크기와 패턴 조밀도에 따른 조명 동공의 형태 변화에 관한 이론적 결과와 투과율 조절 포토마스크를 사용한 웨이퍼 상 CD(critical dimension) 균일도 개선에 관한 실험적 결과에 대해 기술한다. 투과율 조절을 위한 위상 패턴은 패턴이 형성되지 않은 영역에 대해 180$^{\circ}$의 상대적 위상을 갖도록 석영면을 식각한 콘택홀 형태의 패턴을 사용하였다. 콘택홀 패턴의 크기가 작을수록 본래의 조명동공 형태를 유지하게 되며, 동일한 패턴 조밀도에서 더욱 큰 노광 광세기 저하가 일어남을 알 수 있었다. 패턴 조밀도를 위치별로 변화시켜 CD균일도 개선에 적합한 투과율 분포를 포토마스크 후면에 형성하였다. 투과율 조절 포토마스크를 140nm 디자인 롤을 갖고 있는 DRAM(Dynamic Random Access Memory)의 한 주요 레이어에 적용하여 CD 균일도를 3$\sigma$값으로 24.0nm에서 10.7nm 로 개선할 수 있었다.

• 한국전기전자재료학회논문지
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• 제17권12호
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• pp.1264-1270
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• 2004

A fast switching thyristor with a superior trade-off property between the on-state voltage drop and the turn-off time could be fabricated by the proton irradiation method. After making symmetric thyristor dies with a voltage rating of 1,600 V from 350 $\mu$m thickness of 60 $\Omega$ㆍcm NTD-Si wafer and 200 $\mu$m width of n-base drift layer, the local carrier lifetime control by the proton irradiation was performed with help of the HI-13 tandem accelerator in China. The thyristor samples irradiated with 4.7 MeV proton beam showed a superior trade-off relationship of $V_{TM}$ = 1.55 V and $t_{q}$ = 15 $\mu$s attributed to a very narrow layer of short carrier lifetime(～1 $\mu$s) in the middle of its n-base drift region. To explain the small increase of $V_{TM}$ , we will introduce the effect of carrier compensation at the low carrier lifetime region by the diffusion current.ffusion current.t.

• Bulletin of the Korean Chemical Society
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• 제32권12호
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• pp.4371-4376
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• 2011

In this work, we investigate the growth behavior of silicon oxide nanowires via a solid-liquid-solid process. Silicon oxide nanowires were synthesized at $1000^{\circ}C$ in an Ar and $H_2$ mixed gas. A pre-oxidized silicon wafer and a nickel film are used as the substrate and catalyst, respectively. We propose two distinctive growth modes for the silicon oxide nanowires that both act as a unique solid-liquid-solid growth process. We named the two growth mechanisms "grounded-growth" and "branched-growth" modes to characterize their unique solid-liquid-solid growth behavior. The two growth modes were classified by the generation site of the nanowires. The grounded-growth mode in which the grown nanowires are generated from the substrate and the branchedgrowth mode where the nanowires are grown from the side of the previously grown nanowires or at the metal catalyst drop attached at the tip of the nanowire stem.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
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• pp.171-175
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• 2001

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectrics and metal, which can apply to employed in integrated circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of free-defects in inter level dielectrics and metal. Especially, defects like (micro-scratch) lead to severe circuit failure, and affects yield. Current conditioning method - bladder type, orbital pad motion- usually provides unsuitable pad profile during ex-situ conditioning near the end of pad life. Since much of the pad wear occurs by the mechanism of bladder type conditioning and its orbital motion without rotation, we need to implement new ex-situ conditioner which can prevent abnormal regional force on pad caused by bladder-type and also need to rotate the pad during conditioning. Another important study of ADPC is related to the orbital scratch of which source is assumed as diamond grit dropped from the strip during ex-situ conditioning. Scratch from diamond grit damaged wafer severely so usually scraped. Figure 1 shows the typical shape of scratch damaged from diamond. e suspected that intensive forces to the edge area of bladder type stripper accelerated the drop of Diamond grit during conditioning. so new designed Flat stripper was introduced.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2017년도 춘계학술대회 논문집
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• pp.70-70
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• 2017

TSV(through silicon via)는 긴 종횡비를 갖는 패턴에 Cu, Ta, Ti을 높은 conformality를 갖도록 증착하는 공정이다. Magnetron cathode의 자석 배열 설계는 target 물질 종류에 따라서 multitrack, water drop type등이 있으며 target과 substrate 사이의 공간에 플라즈마를 형성시켜서 기판에 이온 입사량을 늘린 후 기판 바이어스를 이용하여 이온 충돌, re-sputtering을 통한 재증착 과정을 통해 치밀한 금속 박막을 연속적으로 형성할 수 있도록 하는 것이 목적이다. 또한 sputter가 사용되고 있는 분야에 효율을 증대시키고, 증착되는 막의 품질향상을 위해 UBMS를 사용하고 있으며, 산업에 사용되어 지는 300 mm wafer용 시스템은 제작비가 약 10억 원 정도 소요되며 다양한 테스트를 진행하기 위해선 많은 비용이 소요된다. 따라서 비용과 소요시간을 줄여 다양한 테스트를 위해 소규모 플라즈마 시스템을 설계하게 되었다. 61 l/sec 터보 분자 펌프와 다이아프램 펌프를 기초로한 TMP station에 2.75 인치 CF flange가 장착된 6 way cross를 main 챔버로 활용하고, 작은 size의 unbalanced magnetron cathode를 제작, 장착한 다음 6 way cross 주변에 전자석을 적절히 배치하여 300 mm wafer system에서와 동일한 물리적 현상을 테스트 할 수 있도록 하였다. Fig1. (a) UBMS system의 사진을 나타내었고, (b)에는 6 way cross 내부에 발생된 플라즈마의 형상을 나타내었다. 전원 장치는 Advanced Energy사의 MDX-1.5K DC power supply를 사용하였고, 방전 전압 - 전류 관계의 가스 압력에 따른 plasma 현상과 magnetron 배율에 따른 plasma 현상 그리고 전자석에 의한 영향을 주로 관찰 하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.67-68
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• 2008

In this study we have developed a packaged silicon carbide power diode with blocking voltage of 2kV. PiN diodes with 7 field limiting rings (FLRs) as an edge termination were fabricated on a 4H-SiC wafer with $30{\mu}m$-thick n-epilayer with donor concentration of $1.6\times10^{15}cm^{-3}$. From packaged PiN diode testing, we obtained reverse blocking voltage of 2kV, forward voltage drop of 4.35V at 100A/$cm^2$, on-resistance of $6.6m{\Omega}cm^2$, and about 8 nanosec reverse recovery time. These properties give a potential for the power system application.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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• pp.271-275
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• 2004

A fast switching thyristor with a superior trade-off property between the on-state voltage drop and the turn-off time could be fabricated by the proton irradiation method. After fabricating symmetric thyristor dies with a voltage rating of 1,600V from $350{\mu}m$ thickness of $60{\Omega}cm$ NTD-Si wafer and $200{\mu}m$ width of N-base drift layer, the local carrier lifetime control by the proton irradiation was performed with help of the HI-13 tandem accelerator in China. The thyristor samples irradiated with 4.7MeV proton beam showed a superior trade-off relationship of $V_{TM}=1.55V\;and\;t_q=15{\mu}s$ attributed to a very narrow layer of short carrier lifetime(${\sim}1{\mu}s$) in the middle of its N-base drift region. To explain the small increase of $V_{TM}$, we will introduce the effect of carrier compensation by the diffusion current at the low carrier lifetime region.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.340-341
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• 2005

Three different composition 130um thickness PZT were fabricated by extrusion method and burned out at $550^{\circ}C$ and sintered at $1260^{\circ}C$/2.5hrs. Actuator was fabricated using glass and Si(100) wafer by MEMS process. From XRD data, in case of DECH, perovskite phase peak strength is higher than others. We were able to obtain the information of grain growth and porosity by SEM images. Also DECH PZT on glass membrane(100um thickness) have larger displacement than others.