• Journal of Power Electronics
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• v.16 no.3
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• pp.925-935
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• 2016

This paper proposes a new interleaved double-input three-level Boost (DITLB) converter, which is composed of two boost converters indirectly in series. Thus, a high voltage gain, together with a low component stress and a small input current ripple due to the interleaved control scheme, is achieved. The operating principle of the DITLB converter under the individual supplying power (ISP) and simultaneous supplying power (SSP) mode is analyzed. In addition, closed-loop control strategies composed of a voltage-current loop and a voltage-balance loop, have been researched to make the converter operate steadily and to alleviate the neutral-point imbalance issue. Experimental results verify correctness and feasibility of the proposed topology and control strategies.

• Journal of Power Electronics
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• v.12 no.5
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• pp.739-747
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• 2012

This paper applies carrier phase shifted pulse-width modulation (CPS-PWM) to transformerless modular multilevel converters (MMC) to improve the output spectrum. Because the MMC topology is characterized by the double-star connection of six legs consisting of cascaded modular chopper cells with floating capacitors, the balance control of the DC-link capacitor voltage is essential for safe operation. This paper presents a leg-balancing control strategy to achieve DC-link voltage balance under all operating conditions. This strategy based on circulating current decoupling control focused on DC-link balancing between the upper and lower legs in each phase pair by considering the six legs as three independent phase-pairs. Experiments are implemented on a 100-V 3-kVA downscaled prototype. The experimental results show that the proposed leg-balancing control is both effective and practical.

• Journal of Power Electronics
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• v.14 no.4
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• pp.661-670
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• 2014

A new DC/DC converter with zero voltage switching is proposed for applications with high input voltage and high load current. The proposed converter has two circuit modules that share load current and power rating. Interleaved pulse-width modulation (PWM) is adopted to generate switch control signals. Thus, ripple currents are reduced at the input and output sides. For high-voltage applications, each circuit module includes two half-bridge legs that are connected in series to reduce switch voltage rating to $V_{in}/2$. These legs are controlled with the use of asymmetric PWM. To reduce the current rating of rectifier diodes and share load current for high-load-current applications, two center-tapped rectifiers are adopted in each circuit module. The primary windings of two transformers are connected in series at the high voltage side to balance output inductor currents. Two series capacitors are adopted at the AC terminals of the two half-bridge legs to balance the two input capacitor voltages. The resonant behavior of the inductance and capacitance at the transition interval enable MOSFETs to be switched on under zero voltage switching. The circuit configuration, system characteristics, and design are discussed in detail. Experiments based on a laboratory prototype are conducted to verify the effectiveness of the proposed converter.

• Journal of Power Electronics
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• v.19 no.1
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• pp.68-78
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• 2019

The emergence of high voltage conversion applications has resulted in a trend of using semiconductor device series associations. Series associations allow for operation at blocking voltages, which are higher than the nominal voltage for each of the semiconductor devices. The main challenge with these topologies is finding a way to guarantee the voltage balance between devices in both blocking and switching transients. Most of the methods that have been proposed to mitigate static and dynamic voltage unbalances result in increased losses within the device. This paper introduces a new series stack topology, where the voltage unbalances are reduced. This in turn, mitigates the switching losses. The proposed topology consists of a circuit that ensures the soft switching of each device, and one auxiliary circuit that allows for switching energy recovery. The principle for the topology operation is presented and experimental tests are performed for two modules. The topology performs excellently for switching transients on each of the devices. The voltage static unbalances were limited to 10%, while the activation/deactivation delay introduced by the lower module IGBT driver takes place in the dynamic unbalances. Thus, the switching losses are reduced by 40%, when compared to hard switching configurations.

• Journal of Power Electronics
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• v.18 no.5
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• pp.1315-1324
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• 2018

A novel three-phase four-wire inverter topology is presented in this paper. This topology is equipped with a special capacitor balance grid without magnetic saturation. In response to unbalanced load and unequal split DC-link capacitors problems, a qusi-full-bridge DC/DC topology is applied in the balance grid. By using a high-frequency transformer, the energy transfer within the two split dc-link capacitors is realized. The novel topology makes the voltage across two split dc-link capacitors balanced so that the neutral point voltage ripple is inhibited. Under the condition of a stable neutral point voltage, the three-phase four-wire inverter can be equivalent to three independent single phase inverters. As a result, the three-phase inverter can produce symmetrical voltage waves with an unbalanced load. To avoid forward transformer magnetic saturation, the voltages of the primary and secondary windings are controlled to reverse once during each switching period. Furthermore, an improved mode chosen operating principle for this novel topology is designed and analyzed in detail. The simulated results verified the feasibility of this topology and an experimental inverter has been built to test the power quality produced by this topology. Finally, simulation results verify that the novel topology can effectively improve the inhibition of an inverter with a three-phase unbalanced load while decreasing the value of the split capacitor.

• The Transactions of the Korean Institute of Power Electronics
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• v.7 no.1
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• pp.65-73
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• 2002

This paper proposes a new carrier-based PWM method to solve the most serious problem of flying capacitor multi-level inverter that is the unbalance of capacitor voltages. The voltage unbalance occurs due to the difference of each capacitor's charging and discharging time applied to Flying Capacitor Inverter. New solution controls the variation of capacitor voltages into the mean '0'during some period by means of new carriers using the leg voltage redundancy in the flying capacitor inverter. The solution can be easily expanded to the multi-level inverter. The leg voltage redundancy in the new method makes the switching loss of device equals to the conduction loss of device. This paper will examine the unbalance of capacitor voltage and the conventional theory of self-balance using Phase-shifted carrier. And then the new method that is suitable to the flying capacitor inverter will be explained.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.1
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• pp.99-104
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• 1999

The large scale industry needs high voltage converters. Therefore series connection of power semiconductor devices is necessary. It is important to prevent the overvoltage from being induced across a device above ratings by the proper voltage balancing in the field of IGBT series connection. In addition, the overvoltage induced by a stray inductance has to be limited in the high power circuit. This paper proposes a new gate control scheme which can balance the voltage properly and limit the overshoot by controlling the slope of collector voltage under the turn-off transient in the series connected IGBTs. The proposed gate control scheme which senses the collector voltage and controls the gate signal actively limits the overvoltage. The new series connected IGBT gate driver is made and its validity is verified by the experimental results in the series connected IGBT circuit.

• Journal of Power Electronics
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• v.9 no.2
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• pp.133-145
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• 2009

In this paper a modular high performance MV-to-LV rectifier based on a cascaded H-bridge rectifier is presented. The proposed rectifier can directly connect to the medium voltage levels and provide a low-voltage and highly-stable DC interface with the consumer applications. The input stage eliminates the necessity for heavy and bulky step-down transformers. It corrects the input power factor and maintains the voltage balance among the individual DC buses. The second stage includes the high frequency parallel-output DC/DC converters which prepares the galvanic isolation, regulates the output voltage, and attenuates the low frequency voltage ripple ($2f_{line}$) generated by the first stage. The parallel-output converters can work in interleaving mode and the active load-current sharing technique is utilized to balance the load power among them. The detailed analysis for modeling and control of the proposed structure is presented. The validity and performance of the proposed topology is verified by simulation and experimental results.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.2
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• pp.301-307
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• 2009

In the paralleled converter module with peak current mode control, current imbalance appears when the voltage controllers with integral control of converter module are not exactly identical. In this paper, the voltage controller is designed to equal the current command of each converter module using the current command bus. The current balance controller is also proposed to balance the average currents of converter modules with imbalaced inductance. It is designed to have good transient response. Proposed method is implemented with the paralleled 2-module and 4-module boost converters with imbalanced inductance. Experimental results verify the performance of current share during both steady and transient states of converter.

• Journal of Power Electronics
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• v.19 no.2
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• pp.487-496
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• 2019

For a solid-state transformer (SST), some factors, such as signal delay, switching loss and differences in the system parameters, lead to unbalanced DC-link voltages among the cascaded H-bridges (CHB). With a control method implemented in the ${\alpha}{\beta}$ frame, the DC-link voltages are balanced, and the reactive power is equally distributed among all of the H-bridges. Based on the ${\alpha}{\beta}$ frame control, the system can achieve independent active current and reactive current control. In addition, the control method of the high-voltage stage is easy to implement without decoupling or a phase-locked loop. Furthermore, the method can eliminate additional current delays during transients and get the dynamic response rapidly without an imaginary current component. In order to carry out the controller design, the vector refactoring relations that are used to balance DC-link voltages are derived. Different strategies are discussed and simulated under the unbalanced load condition. Finally, a three-cell CHB rectifier is constructed to conduct further research, and the steady and transient experimental results verify the effectiveness and correctness of the proposed method.