• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.249-254
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• 2005

This paper presents a system-on-a-chip (SOC) design for digital TV. The single LSI incorporates almost all essential parts such as CPU, ISO/IEC 11172/13818 system/audio/video decoders, a video post-processor, a graphics/OSD processor and a display processor. It has analog IP's inside such as video DACs, an audio PLL, and a system PLL to reduce the system-level implementation cost. Descramblers and Smart Card interface are included to support widely used conditional access systems. The video decoder can decode two video streams simultaneously. The DSP-based audio decoder can process various audio coding specifications. The functional blocks for video quality enhancement also form outstanding features of this SoC. The SoC supports world-wide major DTV services including ATSC, ARIB, DVB, and DIRECTV.

• Journal of Broadcast Engineering
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• v.20 no.6
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• pp.963-966
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• 2015

This paper introduces a programmable multi-format video decoder(MFD) to support HEVC(High Efficiency Video Coding) standard and for other video coding standards. The goal of the proposed MFD is the high-end FHD(Full High Definition) video decoder needed for a DTV(Digital Tele-Vision) SoC(System on Chip). The proposed platform consists of a hybrid architecture that is comprised of reconfigurable processors and flexible hardware accelerators to support the massive computational load and various kinds of video coding standards. The experimental results show that the proposed architecture is operating at a 300MHz clock that is capable of decoding HEVC bit-stream of FHD 30 frames per second.

• Journal of Broadcast Engineering
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• v.16 no.6
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• pp.1018-1025
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• 2011

Scalable Video Coding (SVC) extension of H.264/AVC is a new video coding standard for media convergence by providing diverse videos of different spatial-temporal-quality layers with a single bitstream. Recently, real-time SVC codecs are being developed for the application areas of surveillance video and mobile video, etc. This paper presents the design and implementation of a H.264/SVC decoder based on an embedded DSP using Open SVC Decoder (OSD) which is a real-time software decoder designed for the PC environment. The implementation consists of porting C code of the OSD software from PC to DSP environment, profiling the complexity performance of OSD with further optimization, and integrating the optimized decoder into the TI Davinci EVM (Evaluation Module). 50 QCIF/CIF frames or 15 SD frames per second can be decoded with the implemented DSP-based SVC decoder.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.3
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• pp.511-516
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• 2006

In this raper, we propose the Sequentiel Couleur Avec Memoire or Sequential Color with Memory (SECAM) video encoder system using modified anti-cloche filters and the SECAM video decoder system using a band pass filter (BPF) and an error-free square root. The SECAM encoder requires an anti-cloche filter recommended by International Telecommunication Union-Recommendation (ITU-R) Broadcasting service Television (BT) 470. However, the design of the anti-cloche filter is difficult because the frequency response of the anti-cloche filter is very sharp around rejection-frequency area. So, we convert the filter into a hish pass filter (HPF) by shifting the rejection frequency of 4.286MHz to 0Hz frequency. The design of HPF becomes very easy, compared to that of the anti-cloche filter. The proposed decoder also uses an error-free square root, two differentiators and trigonometric functions to extract color-component information of Db and Dr accurately from frequency modulation (FM) signals in SECAM systems. Also, the BPF in decoder it used for removing color noise in chrominance and dividing CVBS into chrominance and luminance. The proposed systems are experimentally demonstrated with Altera FPGA APEX20KE EP20K1000EBC652-3 device and TV sets.

• Journal of Broadcast Engineering
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• v.24 no.1
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• pp.182-185
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• 2019

This paper analyzes performances of modules in implementing a programmable multi-format video decoder. The goal of the proposed platform is the high-end Full High Definition (FHD) video decoder. The proposed multi-format video decoder consists of a reconfigurable processor, dedicated bit-stream co-processor, memory controller, cache for motion compensation, and flexible hardware accelerators. The experiments suggest performance baseline of modules for the proposed architecture operating at 300 MHz clock with capability of decoding HEVC bit-streams of FHD 30 frames per second.

• ETRI Journal
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• v.44 no.1
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• pp.38-50
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• 2022

This paper presents a study on the use of encoder-derived features in decoder-side depth estimation. The scheme of multiview video encoding does not require the transmission of depth maps (which carry the geometry of a three-dimensional scene) as only a set of input views and their parameters are compressed and packed into the bitstream, with a set of features that could make it easier to estimate geometry in the decoder. The paper proposes novel recursive block splitting for the feature extraction process and evaluates different scenarios of feature-driven decoder-side depth estimation, performed by assessing their influence on the bitrate of metadata, quality of the reconstructed video, and time of depth estimation. As efficient encoding of multiview sequences became one of the main scopes of the video encoding community, the experimental results are based on the "geometry absent" profile from the incoming MPEG Immersive video standard. The results show that the quality of synthesized views using the proposed recursive block splitting outperforms that of the state-of-the-art approach.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.160-162
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• 2014

A programmable video decoding system with multi-core DSP and co-processors is presented. This system is adopted by Digital TV SoC (System on Chip) and is used for FHD HEVC (High Efficiency Video Coding) decoder. Using the DSP based programmable solution, we can reduce commercialization period by one year because we can parallelize algorithm development, software optimization and hardware design. In addition to the HEVC decoding, the proposed system can be used for other application such as other video decoding standard for multi-format decoder or video quality enhancement.

• ETRI Journal
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• v.27 no.5
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• pp.491-496
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• 2005

An application specific processor for an H.264 decoder with a configurable embedded processor is designed in this research. The motion compensation, inverse integer transform, inverse quantization, and entropy decoding algorithm of H.264 decoder software are optimized. We improved the performance of the processor with instruction-level hardware optimization, which is tailored to configurable embedded processor architecture. The optimized instructions for video processing can be used in other video compression standards such as MPEG 1, 2, and 4. A significant performance improvement is achieved with high flexibility. Experimental results show that we could achieve 300% performance for the H.264 baseline profile level 2 decoder.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.295-298
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• 2003

In this paper, a novel maximum a posterion (MAP) estimation for the channel decoding of H.264 codes in the presence of transmission error is presented. Arithmetic codes with a forbidden symbol and trellis search techniques are employed in order to estimate the best transmitted. And, there has been growing interest of communication, the research about transmission of exact data is increasing. Unlike the case of voice transmission, noise has a fatal effect on the image transmission. The reason is that video coding standards have used the variable length coding. So, only one bit error affects the all video data compressed before resynchronization. For reasons of that, channel needs the channel codec, which is robust to channel error. But, usual channel decoder corrects the error only by channel error probability. So, designing source codec and channel codec, Instead of separating them, it is tried to combine them jointly. And many researches used the information of source redundancy In received data. But, these methods do not match to the video coding standards, because video ceding standards use not only one symbol but also many symbols in same data sequence. In this thesis, We try to design combined source-channel codec that is compatible with video coding standards. This MAP decoder is proposed by adding semantic structure and semantic constraint of video coding standards to the method using redundancy of the MAP decoders proposed previously. Then, We get the better performance than usual channel coder's.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.298-300
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• 2004

In the decoding process of interframe wavelet coding, the inverse wavelet transform requires huge computational complexity. However, the decoder may need to be used in various devices such as PDAs, notebooks, PCs or set-top Boxes. Therefore, the decoder's complexity should be adapted to the processor's computational power. A decoder designed in accordance with the processor's computational power would provide optimal services for such devices. So, it is natural that the complexity scalability and the low complexity codec are also listed in the requirements for scalable video coding. In this contribution, we develop a method of controlling and lowering the complexity of the spatial wavelet transform while sustaining almost the same coding efficiency as the conventional spatial wavelet transform. In addition, the proposed method may alleviate the ringing effect for certain video data.