• Title/Summary/Keyword: video compression.

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A Memory-Efficient VLC Decoder Architecture for MPEG-2 Application

  • Lee, Seung-Joon;Suh, Ki-bum;Chong, Jong-wha
    • Proceedings of the IEEK Conference
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    • 1999.11a
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    • pp.360-363
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    • 1999
  • Video data compression is a major key technology in the field of multimedia applications. Variable-length coding is the most popular data compression technique which has been used in many data compression standards, such as JPEG, MPEG and image data compression standards, etc. In this paper, we present memory efficient VLC decoder architecture for MPEG-2 application which can achieve small memory space and higher throughput. To reduce the memory size, we propose a new grouping, remainder generation method and merged lookup table (LUT) for variable length decoders (VLD's). In the MPEG-2, the discrete cosine transform (DCT) coefficient table zero and one are mapped onto one memory whose space requirement has been minimized by using efficient memory mapping strategy The proposed memory size is only 256 words in spite of mapping two DCT coefficient tables.

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FPGA Implementation of Wavelet-based Image Compression CODEC with Watermarking (워터마킹을 내장한 웨이블릿기반 영상압축 코덱의 FPGA 구현)

  • 서영호;최순영;김동욱
    • Proceedings of the IEEK Conference
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    • 2003.07e
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    • pp.1787-1790
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    • 2003
  • In this paper. we proposed a hardware(H/W) structure which can compress the video and embed the watermark in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into H/W with the efficient structure for FPGA. The global operations of the designed H/W consists of the image compression with the watermarking and the reconstruction, and the watermarking operation is concurrently operated with the image compression. The implemented H/W used the 59%(12943) LAB(Logic Array Block) and 9%(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70㎒ clock frequency over. So we verified the real time operation, 60 fields/sec(30 frames/sec).

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Wavelet-compressed Image Improvement Method Using Modification of Wavelet Coefficients (웨이블릿 계수조정을 통한 웨이블릿 압축영상의 화질 개선 방법)

  • 이호근;김윤태;김주원;하영호
    • Proceedings of the IEEK Conference
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    • 2003.07e
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    • pp.1875-1878
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    • 2003
  • This paper Proposes a wavelet-based video compression method to improve compressed images using modification of wavelet coefficients. In conventional wavelet-based compression methods, bigger coefficients are transmitted early according to the significance of the coefficients. In this reason, when some coefficients which have more significance but are not bigger are not transmitted, image degradation occurs. The Proposed method considered two human visual characteristics. First, human eyes are more sensitive to the change of middle frequency which represents abrupt change of brightness than that of high frequency which expresses fine region. Second, human eyes are more dull to color component than luminance respectively. By adjusting the coefficients of wavelet transformed signals and allocating more bits for compression to the luminance signal, higher compression could be achieved.

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Real-Time Video Quality Assessment of Video Communication Systems (비디오 통신 시스템의 실시간 비디오 품질 측정 방법)

  • Kim, Byoung-Yong;Lee, Seon-Oh;Jung, Kwang-Su;Sim, Dong-Gyu;Lee, Soo-Youn
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.46 no.3
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    • pp.75-88
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    • 2009
  • This paper presents a video quality assessment method based on quality degradation factors of real-time multimedia streaming services. The video quality degradation is caused by video source compression and network states. In this paper, we propose a blocky metric on an image domain to measure quality degradation by video compression. In this paper, the proposed boundary strength index for the blocky metric is defined by ratio of the variation of two pixel values adjacent to $8{\times}8$ block boundary and the average variation at several pixels adjacent to the two boundary pixels. On the other hand, unnatural image movement caused by network performance deterioration such as jitter and delay factors can be observed. In this paper, a temporal-Jerkiness measurement method is proposed by computing statistics of luminance differences between consecutive frames and play-time intervals between frames. The proposed final Perceptual Video Quality Metric (PVQM) is proposed by consolidating both blocking strength and temporal-jerkiness. To evaluate performance of the proposed algorithm, the accuracy of the proposed algorithm is compared with Difference of Mean Opinion Score (DMOS) based on human visual system.

A study on application of DCT algorithm with MVP(Multimedia Video Processor) (MVP(Multimedia Video Processor)를 이용한 DCT알고리즘 구현에 관한 연구)

  • 김상기;정진현
    • 제어로봇시스템학회:학술대회논문집
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    • 1997.10a
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    • pp.1383-1386
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    • 1997
  • Discrete cosine transform(DCT) is the most popular block transform coding in lossy mode. DCT is close to statistically optimal transform-the Karhunen Loeve transform. In this paper, a module for DCT encoder is made with TMS320C80 based on JPEG and MPEG, which are intermational standards for image compression. the DCT encoder consists of three parts-a transformer, a vector quantizer and an entropy encoder.

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Design of Fast Search Algorithm for The Motion Estimation using VHDL (VHDL을 이용한 고속 움직임 예측기 설계)

  • 김진연;박노경;진현준;윤의중;박상봉
    • Proceedings of the IEEK Conference
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    • 2000.11d
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    • pp.183-186
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    • 2000
  • Motion estimation technique has been used to increase video compression rates in motion video applications. One of the important algorithms to implement the motion estimation technique is search algorithm. Among many search algorithms, the H.263 adopted the Nearest Neighbors algorithm for fast search. In this paper, motion estimation block for the Nearest Neighbors algorithm is designed on FPGA and coded using VHDL and simulated under the Xilinx foundation environments. In the experiment results, we verified that the algorithm was properly designed and performed on the Xilinx FPGA(XCV300Q240)

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Military surveillance System design using Digital video Recording Camera (디지털 녹화 감시 카메라 시스템에 의한 군사 방위 시스템 설계)

  • 조혜진;홍충효;최연성;김선우
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2003.05a
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    • pp.175-178
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    • 2003
  • In this paper, proposed system use real-time MPEG-2 compression, and retrieve video from the storage using efficient indexed algorithm. System survey wide military range, diffuse situation to adjacent units, and transmit images long distance.

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Post-Processing for Reducing Corner Outliers (Corner outlier 제거를 위한 후처리 기법)

  • 홍윤표;전병우
    • Proceedings of the IEEK Conference
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    • 2003.11a
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    • pp.11-14
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    • 2003
  • In block-based lossy video compression, severe quantization causes discontinuities along block boundaries so that annoying blocking artifacts are visible in decoded video imases. These blocking artifacts significantly decrease the subjective image quality. In order to reduce the blocking artifacts in decoded images, many algorithms have been proposed However studies on so called, corner outliers, have been very limited. Corner outliers make image edges look disconnected from those of neighboring blocks at cross block boundary. In order to solve this problem, we propose a corner outlier detection and compensation algorithm as post-processing in spatial domain The experiment results show that the proposed method provides much improved subjective image quality.

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Implementation of SA-DCT using a datapath (데이터패스를 이용한 SA-DCT 구현)

  • 박주현;김영민
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.35C no.5
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    • pp.25-32
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    • 1998
  • In this paper, SA (shape adaptive)-DCT is implemented using a datapath with 4 MACs (multiplication & accumulator). DCT is a well-known bottleneck of real-time video compression using MPEG-like schemes. High-speed pipelined MACs presented here implement real-time DCT. A datapath in this paper executes DCT/IDCT algorithms for QCIF 15fps(frame per second), maximum rate of VLBV(very low bitrte video) in MPEG-4. A 32bit accumulator in a MAC prevents distortion caused by fixed-point process. It can be applied to various operations such as ME (motion estimation) and MC(motion compensation) with a absolutor and a halfer.

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A fast watermark embedding method for MPEG-2 bit stream (MPEG-2 비트 스트림에 대한 고속 워터마크 삽입방법)

  • 김성일;서정일;김구영;원치선
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 1997.11a
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    • pp.151-154
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    • 1997
  • In this paper, we propose a new watermarking algorithm for copyright protection of video data. The proposed algorithm inserts a watermark directly on the MPEG-2 bitstream. Since more and more video data are stored and transmitted in a compressed form, it is desirable to insert a watermark on the compressed bit stream to avoid the expensive full-decoding and re-encoding process. Embedding a watermark in the compressed domain, we can also avoid the effect of the compression error which may erase the watermark.

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