• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2008.10a
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• pp.367-369
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• 2008

A theoretical model of equivalent drawbead for sheet metal forming analysis is experimentally verified in this paper. After the theoretical drawbead models improved a material description for the accurate calculation of drawbead forces are briefly introduced, they are verified by showing the good agreement of their drawbead forces with experimental measurements. Furthermore, the excellence of theoretical models is demonstrated by the comparison with those of commercial codes.

• Proceedings of the Korean Geotechical Society Conference
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• 1999.03a
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• pp.439-446
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• 1999

In situ experimental studies were Performed at Yongjong Island Geotechnical Experimental Site to evaluate the ground densification on sand deposited. Standard penetration test, cone penetration test, and SASW test were performed and soil profiles and quality of ground improvements were evaluated. The feasibility of applying SASW method were verified by comparing test results. The evaluation technique of in-situ density using SASW and resonant column tests was proposed, and the reliability of proposed method was verified by performing case studies.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.161-164
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• 2000

The architecture of microprocessor for a embedded system should be one that can perform more tasks with fewer instruction codes. The machine codes that high-level language compiler produces are mainly composed of specific ones, and codes that have small size are more frequently used. Extended Instruction Set Architecture (EISC) was proposed for that reason. We have designed pipe-line system for 64 bit EISC microprocessor. function level simulator was made for verification of design and instruction set architecture was also verified by that simulator. The behavioral function of synthesized logic was verified by comparison with the results of cycle-based simulator.

• Proceedings of the Acoustical Society of Korea Conference
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• 1994.06c
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• pp.338-341
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• 1994

In this paper we propose a method to generate a multisyllable onsense wordest for the purpose of synthetic speech assessment and applies th ewordest to assess one commercial text-to-speech system. Some results about the experiment is suggested and it is verified that the generated nonsense wordset can be used to assess the intelligibility of the synthesizer in phoneme level or in phonemic environmental level. From the experimental results it is verified that such multi-syllable nonsense wordset can be useful for the assessment of synthesized speech.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1995.10a
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• pp.889-893
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• 1995

This paper verified error of STL file and presented a new application of reformed division method for reducing to appeared error by using Delaunay triangulation method that used to modify error of verified data. First, it is analyzed each vertices in hole error and classified follow case that is 1. case of plan or slope, 2. case of edge, 3. case of apex and 4. case of rapid curve, and reduced volume tolerance between original model and converted model after convert STL file.

• TTA Journal
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• s.84
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• pp.146-161
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• 2002

TTA(한국정보통신기술협회)는 2002년 10월 8일 (주)이스텔시스템즈(www.eastelsystems.com)의 ATM(asynchronous transfer mode) Router (모델명 : EAR-155)에 대하여 성능 및 aging 시험을 수행하여 국내 최초 TTA Verified 인증서(번호: TTA-V-02-001)를 발급하였다. 본 고에서는 두 대의 EAR-155 ATM Routers를 이용하여 각 라우터의 확장 slot에 Fast Ethernet port, ATM OC3(155 Mbps) port, ATM DS3(44.736 Mbps) port, ATM E1(2.048 Mbps) port 및 TDM E1(2.048 Mbps) port를 장착하여 back-to-back으로 연결한 환경에 대한 no-loss UDP throughput 시험결과를 소개한다.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.333-336
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• 2001

This paper describes the design and implementation results of 40, 32, 24 and 16kbps ADPCM encoder and decoder circuit, based on the protocol CCITT G.726. We verified the ADPCM algorithm using C language and designed the RTL circuit with Verilog HDL. The circuit has been simulated by Verilog-XL, synthesized by Design Compiler and verified using Xilinx FPGA. Since the synthesized circuit includes a small number of gates, it is expected to be used as a core module in the digital voice and image processing SOC.

• TTA Journal
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• s.87
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• pp.169-173
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• 2003

TTA(한국정보통신기술협회)는 2003년 4월 30일 ㈜엠시스(http://www.msys.tv)의 MPEG Player(모델명 : MSY200)의 기능 및 성능시험을 수행하여 TTA Verified 인증서(번호 : TTA-V-B-03-001)을 발급하였다. 위의 장비는 MPEG Player의 기본 기능인 Play, Record 외에 스트림 정보를 전면 LCD 창을 통해 확인할 수 있는 기능을 제공하며, 4개의 독자적인 물리채널 운용으로 Play, Record 등의 기능을 4 채널에서 동시에 독립적으로 동작시키는 것이 가능하고, 국제기준 PCR 정확도 및 균일 출력 비트율을 만족하였으며, 장시간 사용 동작 시험에서도 양호한 동작상태를 보장할 수 있는 성능을 나타내었다.

• TTA Journal
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• s.86
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• pp.83-88
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• 2003

TTA(한국정보통신기술협회, 사무총장 임주환)에서 제공하고 있는 무선랜 장비 TTA Verified 시험은 KT 및 하나로통신의 Benchamarking Test(BMT)의 참가자격 요건으로 Wi-Fi 인증과 함께 공인되고 있는 인증시험으로써, 올해 1월부터 본격적인 시험인증 서비스를 진행해왔다. 본 고에서는 지난 2월과 3월에 걸쳐 진행된 무선랜 TTA Verified 인증시험의 내용 및 결과에 대해서 분석하고 TTA 무선랜 상호운용성 인증마크를 획득한 무선랜 Access Point (AP) 와 Station에 대해서 소개하고자 한다.

• Proceedings of the IEEK Conference
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• 2002.06d
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• pp.171-174
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• 2002

This paper presents an implementation method of phasor measurement device, which is based on the FPGA implementation of the sliding-DFT The design is verified by the timing simulation of its operation. The error effect of coefficient approximation and frequency deviation in the recursive implementation of the sliding-DFT is analytically derived and verified with the computer simulations.