• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.2
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• pp.260-267
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• 2015

An LCL-type isolated dc-dc converter is analyzed, using ac approximation. Analyses to express characteristics on the proposed converter are derived under steady and ideal elements conditions in this paper. The two operating modes can be identified from the analysis results representing different device conduction sequences. This converter is capable of achieving required output voltage(step up or down) operations with inductance ratio while operated at fixed frequency with constant duty ratio-50%. Experimental results show that the designed converter based on Q has zero voltage switching and constant output voltage at different load variations to verify the analysis.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.8C
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• pp.806-815
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• 2006

It is studied to design a low pass filter of the SRC(sample rate converter), which is used to change the sampling rate of digital signals such as in digital modulation and demodulation systems. The larger the conversion ratio of the sample rate becomes, the more signal processing is needed for the filter, which corresponds to the more complexity in circuit realization. Thus it is important to reduce the amount of signal processing for the case of high conversion ratio. In this paper it is presented a design method of a two-stage cascaded FIR filter, which proved to have reduced amount of signal processing in comparison with a conventional single-stage one. The reduction effect of signal processing turned out to be more noticeable for larger value of conversion ratio, for instance, giving down to 72% in complexity for the conversion ratio of 32. It has been shown that the reduction effect is dependent to specific combination of conversion ratios of the cascaded filters. So an exhaustive search has been performed in order to obtain the optimal combination for various values of the total conversion ratio. In this paper every filter is considered to be implemented in the form of a polyphase FIR filter, and its coefficients are determined by use of the Parks-McCllelan algorithm.

• Journal of Power Electronics
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• v.9 no.6
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• pp.835-844
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• 2009

In this paper a new buck-boost type DC-DC converter is presented. Its voltage gain is positive, all active elements operate under soft-switching condition independent of loading, magnetic isolation and self output short-circuit protection exist, and very fast dynamic operation is achievable by a simple bang-bang controller. This converter also exhibits appropriate PFC characteristics since its input current is inherently proportional to the source voltage. When the voltage source is off-line, it is sufficient to add an inductor after the rectifier, then near unity power factor is achievable. All essential guidelines to design the converter as a DC-DC and a PFC regulator are presented. Simulation and experimental results verify the developed theoretical analysis.

• Journal of Electrical Engineering and Technology
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• v.11 no.4
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• pp.860-868
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• 2016

A bidirectional DC-DC converter (BDC) is an indispensable electrical unit for the electric vehicles (EVs). High efficiency, high power density, isolation, light weight and reliability are all essential requirements for BDC. In this paper, a 3 kW BDC for the battery charger of EVs is proposed. The proposed converter consists of a half-bridge structure on the primary side and an isolation transformer and a synchronous rectifier structure on the secondary side. With this topology, minimum number of switching devices are required for bidirectional power flow between the two dc buses of EVs. The easy implementation of the synchronous rectification gives advantages in terms of efficiency, cost and flexibility. The proposed BDC achieves high efficiency when operating in both modes (step-up and step-down). A 3 kW prototype is implemented to verify theoretical analysis and the performance of the proposed converter.

• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.160-162
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• 2020

A control technique for the auxiliary buck/boost converter is proposed herein to improve the load transient response of the buck converter. The proposed technique improves the system efficiency by enabling the soft switching operation of the auxiliary converter. The design guidelines for achieving capacitor charge balance for the output capacitor during the transient are also presented herein. The experimental results revealed that the output voltage undershoot and settling time during the load step-up transient were 40 mV and 14 ㎲, respectively, and the output voltage overshoot and settling time during the load step-down transient were 35 mV and 21 ㎲, respectively. The performance and effectiveness of the proposed technique were experimentally verified using a prototype buck converter with a 15-V input, 3.3-V output, and 200-kHz switching frequency.

• International Journal of Naval Architecture and Ocean Engineering
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• v.9 no.3
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• pp.239-245
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• 2017

As a new technical approach, wave energy converter by using vertical motion of water in the multiple water chambers were developed to realize actual wave power generation as eco-environmental renewable energy. And practical use of wave energy converter was actually to require the following conditions: (1) setting up of the relevant device and its application to wave power generation in case that severe wave loading is avoided; (2) workability in installation and maintenance operations; (3) high energy conversion potential; and (4) low cost. In this system, neither the wall(s) of the chambers nor the energy conversion device(s) are exposed to the impulsive load due to water wave. Also since this system is profitable when set along the jetty or along a long floating body, installation and maintenance are done without difficulty and the cost is reduced. In this paper, we describe the system which consists of a float, a shaft connected with another shaft, a rack and pinion arrangement, a ratchet mechanism, and rotary type generator(s). Then, we present the dynamics model for evaluating the output electric power, and the results of numerical calculation including the effect of the phase shift of up/down motion of the water in the array of water chambers aligned along the direction of wave propagation.

• Journal of Advanced Marine Engineering and Technology
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• v.39 no.8
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• pp.821-827
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• 2015

This study concentrates on a wave energy converter with floaters that extracts the ocean's energy by moving up and down with the wave motion. The floater is connected to an arm structure, including a hydraulic cylinder that drives a hydraulic generator. This study focuses on a structural analysis of the floater unit, including arm and cylinder components, platform and jack-up system, along with spud columns. Previous studies have been conducted for miniature models for experimentation, but this study focuses on the full-scale model structural analysis. Static structural analysis is conducted using fine numerical grids. Due to the complexity of the whole model, it is analyzed in separate pieces. The floater unit, with arm and cylinder, are combined into one system. The platform is analyzed separately as a single system. There are four jack-up systems for each spud column; only one jack-up system is analyzed, as uniform loads are assumed on each system. There are several load cases for each system, all of which are analyzed thoroughly for stress (von Mises, shear, and normal) and deformation. Acceptable results were obtained for most of the components; unsafe components were redesigned.

• ETRI Journal
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• v.29 no.4
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• pp.463-469
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• 2007

A phase-locked loop (PLL) is described which is operable from 0.4 GHz to 1.2 GHz. The PLL has basically the same architecture as the conventional analog PLL except the locking information is stored as digital code. An analog-to-digital converter is embedded in the PLL, converting the analog loop filter output to digital code. Because the locking information is stored as digital code, the PLL can be turned off during power-down mode while avoiding long wake-up time. The PLL implemented in a 0.18 ${\mu}m$ CMOS process occupies 0.35 $mm^2$ active area. From a 1.8 V supply, it consumes 59 mW and 984 ${\mu}W$ during the normal and power-down modes, respectively. The measured rms jitter of the output clock is 16.8 ps at 1.2 GHz.

• Proceedings of the KIEE Conference
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• 2002.11d
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• pp.3-11
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• 2002

This paper presents the trend of low voltage and high current technology for DC-DC converters. It can be said that the output voltage of the on-board power supply has been rapidly moving forward a low voltage in proportion to the minuteness of the semiconductors. As for as its speed is concerned, the change of the market situation seems to be faster than that of R&D for the low voltage and high current products put out by power supply manufacturers. Here, the present situation and the trend of non-isolated type step-down DC-DC converter and isolated type DC-DC converter called "Brick" will be taken up mainly from the fellowing point of view. -low voltage and high current keeping up with the current demand for the latest telecommunication networks and broadband. -build-up of the total solution for dispersion system power supply. In this paper, an explanation is given to mainly concerning to the newest products in the supplier's position.

• Journal of Power Electronics
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• v.16 no.2
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• pp.447-454
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• 2016

A single-ended primary-inductor converter (SEPIC) features low input current ripple and output voltage up/down capability. However, the switching devices in a two-level SEPIC suffer from high voltage stresses and switching losses. To cope with this drawback, this study proposes a three-level SEPIC that uses a low voltage-rated switch and thus achieves better switching performance compared with the two-level SEPIC. The three-level SEPIC can reduce switch voltage stresses and switching losses. The converter operation and control method are described in this work. The experimental results for a 500 W prototype converter are also discussed. Experimental results show that unlike the two-level SEPIC, the three-level SEPIC achieves improved power efficiency with balanced capacitor voltages.