• 제목/요약/키워드: two-level

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A Study on Developing Fold-Over Designs with Four-Level Quantitative Factors (4-수준 계량인자가 포함된 반사계획에 관한 연구)

  • Choi, Kiew-Phil;Byun, Jai-Hyun
    • Journal of Korean Institute of Industrial Engineers
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    • v.28 no.3
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    • pp.283-290
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    • 2002
  • Two-level fractional factorial designs are widely used when many factors are considered. When two-level fractional factorial designs are used, some effects are confounded with each other. To break the confounding between effects, we can use fractional factorial designs, called fold-over designs, in which certain signs in the design generators are switched. In this paper, optimal fold-over designs with four-level quantitative and two-level factors are presented for (1) the initial designs without curvature effect and (2) those with curvature effect. Optimal fold-over design tables are provided for 8-run, 16-run, and 32-run experiments.

A Look-Up Table Based Error Diffusion Algorithm for Dynamic False Contour Reduction of Plasma Display Panels

  • Lee, Ho-Seop;Kim, Choon-Woo
    • Journal of Information Display
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    • v.2 no.2
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    • pp.32-38
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    • 2001
  • PDP(plasma display panel) represents the gray levels by the pulse number modulation technique that results in undesirable dynamic false contours on moving images. This paper proposes a LUT(Look-up table) based error diffusion algorithm for reduction of the dynamic false contours. A quantitative measure of the dynamic false contours is defined first. The measure of the dynamic false contours is calculated through simulation of every gray level combination of two consecutive frames. Based on the calculated measures, a modified gray level for a pair of gray levels of two consecutive frames is chosen to reduce the dynamic false contours. The chosen gray levels serve as contents of a gray level conversion LUT. Given a pair of gray levels of two consecutive frames, the gray level of current frame is modified based on the gray level conversion LUT. The new gray level is displayed on PDP. An error diffusion algorithm is, then, applied to compensate for the differences in the gray levels.

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Zero-voltage-switching three level auxiliary resonant commutated pole inverter (영전압 스위칭 3-레벨 보조 공진 폴 인버터)

  • 유동욱;원충연;조정구;백주원
    • The Transactions of the Korean Institute of Electrical Engineers
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    • v.45 no.4
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    • pp.535-542
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    • 1996
  • A zero voltage switching (ZVS) three level auxiliary resonant commutated pole inverter (ARCPI) is presented for high power GTO inverters. The concept of ARCP for two level inverter is extended to the three inverter. The proposed auxiliary commutation circuit consists of one resonant inductor and two bi-directional switches, which provides ZVS condition to the main devices without increasing device voltage or current stresses. The auxiliary device operates with zero current switching (ZCS) which enables use of the low cost thyristors. The proposed ARCPI can handle higher voltage and higher power (1-10MVA) comparing to the two level one. Operation and analysis of the ARCPI are illustrated and the features are compared o those of the snubber circuit incorporated three level inverter. Experimental results with 10kW, 4kHz prototype are presented to verify the principle of operation. (author). refs., figs., tab.

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Synchronous Visible Light Communication Systems Using 3-Level LED Modulation (3-Level LED 변조를 이용한 동기식 가시광통신 시스템)

  • Lee, Seong-Ho
    • Journal of Sensor Science and Technology
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    • v.22 no.6
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    • pp.421-427
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    • 2013
  • In this paper, we introduce a new synchronous visible light communication system in which the synchronizing pulse and the data bits are simultaneously transmitted using a 3-level light signal. In the transmitter, the synchronizing pulse and the data bits modulate independently two identical visible LEDs, whose output lights add in free space, make 3-level optical signal. In the receiver, a photodiode detects the light and generates a 3-level output voltage, whose positive and negative part correspond to the synchronizing pulse and the data bits, respectively. The two signals are easily separated and recovered by a simple diode circuit. This configuration provides two independent VLC channels without any multiplexing technique, simplifies the circuit design and construction of synchronous VLC systems.

SOME CONSTRUCTION OF ALL LEVEL ARTINIAN O-SEQUENCES OF SOCLE DECREE 5 AND TYPE 3

  • Shin, Dong-Soo;Shin, Yong-Su
    • Journal of applied mathematics & informatics
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    • v.11 no.1_2
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    • pp.317-326
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    • 2003
  • We classify all possible level Artinian O-sequences of socle degree 5 and type 3. Moreover, we show how to construct level Artinian algebras with those Hilbert functions using the sum of two ideals of finite sets of points in $P^2$ such that the ideal of the union of two sets is level.

Shape Optimization of Plane Truss Structures (평면(平面)트러스 구조물(構造物)의 형상최적화(形狀最適化))

  • Kim, Soung Wan;Lee, Gyu Won
    • KSCE Journal of Civil and Environmental Engineering Research
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    • v.6 no.2
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    • pp.1-15
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    • 1986
  • The algorithm Proposed utilizes the two-levels technique. In the first level which consists of two phases, the cross-sectional area of the truss member is optimized by transforming the nonlinear problem into SUMT, and solving SUMT utilizing the modified Newton-Rahson method. In the second level, the geometric shape is optimized utilizing the unindirectional search technique of the Powell method which make it possible to minimize only the objective function. The algorithm Proposed in this study is numerically tested for several truss structures with various shapes, loading conditions and design criteria, and compared with the results of the other algorithms to examine its applicability and stability. The numerical comparisons show that the two-Levels algorithm Proposed in this study is safely applicable to any design criteria, and the convergency rate is relathely fast and stable compared with other iteration methods for the geometric optimization of truss structures.

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Comparison of DTC between two-level and three-level inverters for LV propulsion electric motor in ship (선박 추진용 저압 전동기에 대한 2레벨 및 3레벨 인버터의 직접토크제어 비교)

  • Ki-Tak RYU;Jong-Phil KIM;Yun-Hyung LEE
    • Journal of the Korean Society of Fisheries and Ocean Technology
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    • v.60 no.1
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    • pp.71-79
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    • 2024
  • In compliance with environmental regulations at sea and the introduction of unmanned autonomous ships, electric propulsion ships are garnering significant attention. Induction machines used as propulsion electric motor (PEM) have maintenance advantages, but speed control is very complicated and difficult. One of the most commonly used techniques for speed control is DTC (direct torque control). DTC is simple in the reference frame transformation and the stator flux calculation. Meanwhile, two-level and three-level voltage source inverters (VSI) are predominantly used. The three-level VSI has more flexibility in voltage space vector selection compared to the two-level VSI. In this paper, speed is controlled using the DTC method based on the specifications of the PEM. The speed controller employs a PI controller with anti-windup functionality. In addition, the characteristics of the two-level VSI and three-level VSI are compared under identical conditions. It was confirmed through simulation that proper control of speed and torque has been achieved. In particular, the torque ripple was small and control was possible with a low DC voltage at low speed in the three-level VSI. The study confirmed that the application of DTC, using a three-level VSI, contributes to enhancing the system's response performance.

An Algorithm for the Assignment of the Two-Level Factors on the Table of the Orthogonal Arrays (2수준 직교배열표의 요인 배치 방법)

  • 박명규
    • Journal of Korean Society of Industrial and Systems Engineering
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    • v.10 no.16
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    • pp.81-88
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    • 1987
  • This article develops to determine and to allocate the two level factors at the table of orthogonal arrays. The column numbers of two factors and two-factor interaction can be determined in applying the bit-by-bit EX-OR operation. The assignment of the Two factors and Two factor interaction is attained by USING COMPUTER, IBM PC/AT applying algorithm of EX-OR operation Theory.

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The Developments of State CHDL and Two-Level Minimizer for State Machine Synthesizer (상태합성기(State Machine Synthesizer) 설계를 위한 상태 CHDL 개발 및 Two-level minimizer 개발에 관한 연구)

  • 김희석;이근만;임인칠
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.29A no.4
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    • pp.83-90
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    • 1992
  • The state machine synthesizer is widely used to FSM synthesis. In this paper, we developed the state machine description language "state CHDL" such as IF, THEN, ELSE, SWITCH, CASE statements. Also, an algorithm for efficient state minimization and two level minimizer of FSM and graphical user interface-pin map window, supporting the designer with input-ouput effency, are presented.

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Guideline of Acceleration Length by Level of Service for Two Lane Entrance Ramp (2차선 유입연결로의 서비스 수준별 가속차선 길이 산정 기준)

  • 문대승;장명순
    • Journal of Korean Society of Transportation
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    • v.14 no.3
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    • pp.75-90
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    • 1996
  • The objective of study is to examine relationship between traffic flow characteristics of two lane entrance terminal and acceleration length, and to suggest the acceleration length by level of service. The relationship between the speed ratio and the distance from the ramp appeared to be a quadratic concave from. In the case of two lane entrance ramp, the acceleration length is suggested as 1.4~2.0 times longer than the acceleration length of one lane entrance ramp. It is also recommended that acceleration length for two lane entrance ramp should be designed according to the level of service at the right most lane (level of service A : 1.4 B : 1.6 C : 1.8 D : 2.0 times of the one lane entrance ramp acceleration length) on freeway.

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