• Title/Summary/Keyword: turbo decoder

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Performance of Iterative Multiuser Detector and Turbo Decoder in WCDMA System (WCDMA 시스템에l서 반복 다중사용자 검출기 및 터보 복호기의 성능)

  • Kim, Jeong-Goo
    • Journal of Korea Society of Industrial Information Systems
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    • v.11 no.4
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    • pp.40-46
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    • 2006
  • The performance of iterative multiuser detector and turbo decoder is presented to provide high quality multimedia services in WCDMA (wideband code division multiple access) system in this paper. Especially the relationship between the local iteration of turbo decoder and the global iteration of multiuser detector including the turbo decoder is analyzed. As a result, three local iterations and three global iterations are considered to be sufficient to provide satisfactory error performance with resonable complexity. The interference cancellation capability of global iteration is improved when the number of users is increased.

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Low Complexity Decoder for Space-Time Turbo Codes

  • Lee Chang-Woo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.4C
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    • pp.303-309
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    • 2006
  • By combining the space-time diversity technique and iterative turbo codes, space-time turbo codes(STTCS) are able to provide powerful error correction capability. However, the multi-path transmission and iterative decoding structure of STTCS make the decoder very complex. In this paper, we propose a low complexity decoder, which can be used to decode STTCS as well as general iterative codes such as turbo codes. The efficient implementation of the backward recursion and the log-likelihood ratio(LLR) update in the proposed algorithm improves the computational efficiency. In addition, if we approximate the calculation of the joint LLR by using the approximate ratio(AR) algorithm, the computational complexity can be reduced even further. A complexity analysis and computer simulations over the Rayleigh fading channel show that the proposed algorithm necessitates less than 40% of the additions required by the conventional Max-Log-MAP algorithm, while providing the same overall performance.

VLSI Design of SOVA Decoder for Turbo Decoder (터보복호기를 위한 SOVA 복호기의 설계)

  • Kim, Ki-Bo;Kim, Jong-Tae
    • Proceedings of the KIEE Conference
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    • 2000.07d
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    • pp.3157-3159
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    • 2000
  • Soft Output Viterbi Algorithm is modification of Viterbi algorithm to deliver not only the decoded codewords but also a posteriori probability for each bit. This paper presents SOVA decoder which can be used for component decoder of turbo decoder. We used two-step SMU architectures combined with systolic array traceback methods to reduce the complexity of the design. We followed the specification of CDMA2000 system for SOVA decoder design.

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Parameter Optimization of SOVA for the 3GPP complied Turbo code (3GPP 규격의 터보 복호기구현을 위한 SOVA 파라미터 최적화)

  • 김주민;고태환;정덕진
    • Proceedings of the IEEK Conference
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    • 2000.11a
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    • pp.157-160
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    • 2000
  • In order to design a low complexity and high performance SOVA decoder for Turbo Codes, we need to analyze the decoding performance with respect to several important design parameters and find out optimal values for them. Thus, we use a scaling factor of soft output and a update depth as the parameters and analyze their effect on the BER performance of the SOVA decoder. finally, we shows the optimal values of them for maximum decoding performance of SOVA decoder for 3GPP complied Turbo codes.

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Efficient Low-Power Turbo Decoder (효율적인 저전력 터보 복호기)

  • 배성일;김재석
    • Proceedings of the IEEK Conference
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    • 1999.06a
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    • pp.73-76
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    • 1999
  • In this paper, we propose a new design of turbo decoder. It contains the simple additional unit which automatically decides the number of the iteration by detecting of the reliability value as threshold value. We investigate the relationship between the reliability value and the number of the iteration. We find the optimal threshold value without noticeable loss in performance. As a results of the simulation, it reduces the average number of the iteration compared with the conventional turbo decoder.

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A Study on the Structure of Turbo Trellis Coded Modulation with an Effectively Reduced Complexity in Wireless Communication Channel (무선통신채널에서 효과적으로 감소된 복잡도를 갖는 Turbo Trellis Coded Modulation 구조 연구)

  • Kim Jeong-su
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.5 no.5
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    • pp.409-412
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    • 2004
  • This paper shows that the proposed Turbo TCM(Turbo Trellis Coded Modulation) has a good performance with a little complexity of decoder. The encoder structure, which is connected with Turbo Codes, is the proposed modulation technique for an efficient bandwidth, This method is used symbol by symbol MAP decoder of iteration similar to binary Turbo Codes in the receiver. The result shows that the BER performance according to iteration is improved about 2,5dB at $BER=10^{-2}$ compared to Turbo Codes with Gray mapping.

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A Turbo-Coded Modulation Scheme for Deep-Space Optical Communications (Deep-Space 광통신을 위한 터보 부호화 변조 기법)

  • Oh, Sang-Mok;Hwang, In-Ho;Lee, Jeong-Woo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.2C
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    • pp.139-147
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    • 2010
  • A novel turbo coded modulation scheme, called turbo-APPM, for deep space optical communications is constructed. The constructed turbo-APPM is a serial concatenations of turbo codes, an accumulator and a pulse position modulation (PPM), where turbo codes act as an outer code while the accumulator and the PPM act together as an inner code. The generator polynomial and the puncturing rule for generating turbo codes are chosen to show the low bit error rate. At the receiver, the joint decoding is performed by exchanging soft information iteratively between the inner decoder and the outer decoder. In the outer decoder, a local iterative decoding for turbo codes is conducted before transferring soft information to the inner decoder. Poisson distribution is used to model the deep space optical channel. It is shown by simulations that the constructed turbo-APPM provides coding gains over all previously proposed schemes such as LDPC-APPM, RS-PPM and SCPPM.

An FPGA Design of High-Speed Turbo Decoder

  • Jung Ji-Won;Jung Jin-Hee;Choi Duk-Gun;Lee In-Ki
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.6C
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    • pp.450-456
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    • 2005
  • In this paper, we propose a high-speed turbo decoding algorithm and present results of its implementation. The latency caused by (de)interleaving and iterative decoding in conventional MAP turbo decoder can be dramatically reduced with the proposed scheme. The main cause of the time reduction is to use radix-4, center to top, and parallel decoding algorithm. The reduced latency makes it possible to use turbo decoder as a FEC scheme in the real-time wireless communication services. However the proposed scheme costs slight degradation in BER performance because the effective interleaver size in radix-4 is reduced to an half of that in conventional method. To ensure the time reduction, we implemented the proposed scheme on a FPGA chip and compared with conventional one in terms of decoding speed. The decoding speed of the proposed scheme is faster than conventional one at least by 5 times for a single iteration of turbo decoding.

(Turbo Decoder Design with Sliding Window Log Map for 3G W-CDMA) (3세대 이동통신에 적합한 슬라이딩 윈도우 로그 맵 터보 디코더 설계)

  • Park, Tae-Gen;Kim, Ki-Hwan
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.9 s.339
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    • pp.73-80
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    • 2005
  • The Turbo decoders based on Log-MAP decoding algorithm inherently requires large amount of memory and intensive complexity of hardware due to iterative decoding, despite of excellent decoding efficiency. To decrease the large amount of memory and reduce hardware complexity, the result of previous research. And this paper design the Turbo decoder applicable to the 3G W-CDMA systems. Through the result of previous research, we decided 5-bits for the received data 6-bits for a priori information, and 7-bits for the quantization state metrics. The error correction term for $MAX^{*}$ operation which is the main function of Log-MAP decoding algorithm is implemented with very small hardware overhead. The proposed Turbo decoder is synthesized in $0.35\mu$m Hynix CMOS technology. The synthesized result for the Turbo decoder shows that it supports a maximum 9Mbps data rate, and a BER of $10^{-6}$ is achieved(Eb/No=1.0dB, 5 iterations, and the interleaver size $\geq$ 2000).

An FPGA Implementation of High-Speed Flexible 27-Mbps 8-StateTurbo Decoder

  • Choi, Duk-Gun;Kim, Min-Hyuk;Jeong, Jin-Hee;Jung, Ji-Won;Bae, Jong-Tae;Choi, Seok-Soon;Yun, Young
    • ETRI Journal
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    • v.29 no.3
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    • pp.363-370
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    • 2007
  • In this paper, we propose a flexible turbo decoding algorithm for a high order modulation scheme that uses a standard half-rate turbo decoder designed for binary quadrature phase-shift keying (B/QPSK) modulation. A transformation applied to the incoming I-channel and Q-channel symbols allows the use of an off-the-shelf B/QPSK turbo decoder without any modifications. Iterative codes such as turbo codes process the received symbols recursively to improve performance. As the number of iterations increases, the execution time and power consumption also increase. The proposed algorithm reduces the latency and power consumption by combination of the radix-4, dual-path processing, parallel decoding, and early-stop algorithms. We implement the proposed scheme on a field-programmable gate array and compare its decoding speed with that of a conventional decoder. The results show that the proposed flexible decoding algorithm is 6.4 times faster than the conventional scheme.

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