• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.34-34
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• 2009

The electrical characteristics of tunnel barrier engineered charge trap flash (TBE-CTF) memory with $SiO_2/Si_3N_4/SiO_2/Si$ engineered tunnel barrier, $HfO_2$ charge trap layer and $Al_2O_3$ blocking oxide layer (MAHONOS) were investigated. The energy bad diagram was designed by using the quantum-mechanical tunnel model (QM) and then the CTF memory devices were fabricated. As a result, the best thickness combination of MAHONOS is confirmed. Moreover, not enhanced P/E speed (Program: about $10^6$ times) (Erase: about $10^4$ times) but also enhanced retention and endurance characteristics are represented.

• Electrical & Electronic Materials
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• v.7 no.6
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• pp.473-480
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• 1994

The electron tunnel effect in polvimide LB films sandwiched between metal electrodes has been investigated in the present work by a study of both the elastic and inelastic tunneling components. By the results of elastic tunneling experiments in Au/Pl/Au tunneling junction, we can judge the height and thickness of tunnel barrier. The inelastic current in Inelastic Electron Tunneling Spectroscopy(IETS) is due to the interaction of the tunneling electron with the vibrational modes of the molecular species in the barrier. Measurements are done on Au/PI/Pb tunneling junctions. The spectra obtained are the second derivatives of the current-voltage characteristics of these junctions : specifically, d$^{2}$1/dV$^{2}$ as a function of voltage V. Because the energies measured by IETS can be directly compared to those measured by infrared and Raman spectroscopy, IR-RAS spectroscopy also measured for reference.

• Journal of Magnetics
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• v.15 no.4
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• pp.185-189
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• 2010

Spin polarized tunneling through a hybrid tunnel barrier of a Spin filter (SF) based on a EuO ferro-magnetic semiconductor and an organic semiconductor (OSC) (rubrene in this case) was investigated. For quasi-magnetic tunnel junction (MTJ) structures, such as Co/rubrene/EuO/Al, we observed a strong spin filtering effect of the EuO layer exhibiting I-V curves with high spin polarization (P) of up to 99% measured at 4 K. However, a magnetoresistance (MR) value of 9% was obtained at 4.2 K. The low MR compared to the high P could be attributed to spin scattering caused by structural defects at the interface between the EuO and rubrene, due to nonstoichiometry in the EuO.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.53-53
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• 2009

Charge trap flash memory devices with modified tunneling barriers were fabricated using the tunneling barrier engineering technique. Variable oxide thickness (VARIOT) barrier and CRESTED barrier consisting of thin $SiO_2$ and $Si_3N_4$ dielectric layers were used as engineered tunneling barriers. The VARIOT type tunneling barrier composed of oxide-nitride-oxide (ONO) layers revealed reliable electrical characteristics; long retention time and superior endurance. On the other hand, the CRESTED tunneling barrier composed of nitride-oxide-nitride (NON) layers showed degraded retention and endurance characteristics. It is found that the degradation of NON barrier is associated with the increase of interface state density at tunneling barrier/silicon channel by programming and erasing (P/E) stress.

• Proceedings of the Korean Magnestics Society Conference
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• 2007.05a
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• pp.215.1-215.1
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• 2007

• Proceedings of the Korean Magnestics Society Conference
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• 2002.04a
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• pp.44-45
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• 2002

• Proceedings of the Korean Magnestics Society Conference
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• 2004.06a
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• pp.150-151
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• 2004

• Proceedings of the Korean Magnestics Society Conference
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• 2001.10a
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• pp.58-59
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• 2001

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.24-25
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• 2008

The effect of heat treatment in $HfO_2$ as charge trap with $SiO_2/Si_3N_4/SiO_2$ as tunnel oxide layer in capacitors has been investigated. Rapid thermal annealing (RTA) were carried out at the temperature range of 600 - $900^{\circ}C$. It is found that all devices carried out heat treatment have large threshold voltage shift Especially, device performed heat treatment at $900^{\circ}C$ has been confirmed the largest memory window. Also, Threshold voltage shift of device used conventional $SiO_2$ as tunnel oxide layer was smaller than that with $SiO_2/Si_3N_4/SiO_2$.

• Journal of the Korean Magnetics Society
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• v.15 no.4
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• pp.231-235
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• 2005

We studied the microstructural evolution of ZrTM-Al (TM=Nb and Ti) alloy films, MR and electrical properties of the MTJ with $ZrTM-AlO_x$ barrier as a function of Zr/TM ratio. We observed that the ternary-oxide barrier reduced the TMR ratio due mainly to the structural defects such as the surface roughness. The change in TMR ratio and $V_h$ with Zr/TM ratio exactly corresponds to the systematic changes in the microstructural variation. Although the MTJ with ternary oxide reduced the TMR and the electrical stabilities, the junction resistances decreased as the Ti and Nb concentration increased due to the band-gap reduction caused by the formation of extra bands