• Title/Summary/Keyword: tristate

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Viewing Angle Switching of Tristate Liquid Crystal Display

  • Chen, Chao Ping;Jhun, Chul-Gyu;Yoon, Tae-Hoon;Kim, Jae-Chang
    • 한국정보디스플레이학회:학술대회논문집
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    • 2007.08a
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    • pp.391-394
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    • 2007
  • A tristate liquid crystal display characterized by two distinct dark states and one bright state has been presented. These two dark states contribute to two different viewing angles. We demonstrate a single panel of vertically aligned cell whose viewing angles can be directly selected from two sets of driving voltage.

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Area- and Energy-Efficient Ternary D Flip-Flop Design

  • Taeseong Kim;Sunmean Kim
    • Journal of Sensor Science and Technology
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    • v.33 no.3
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    • pp.134-138
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    • 2024
  • In this study, we propose a ternary D flip-flop using tristate ternary inverters for an energy-efficient ternary circuit design of sequential logic. The tristate ternary inverter is designed by adding the functionality of the transmission gate to a standard ternary inverter without an additional transistor. The proposed flip-flop uses 18.18% fewer transistors than conventional flip-flops do. To verify the advancement of the proposed circuit, we conducted an HSPICE simulation with CMOS 28 nm technology and 0.9 V supply voltage. The simulation results demonstrate that the proposed flip-flop is better than the conventional flip-flop in terms of energy efficiency. The power consumption and worst delay are improved by 11.34% and 28.22%, respectively. The power-delay product improved by 36.35%. The above simulation results show that the proposed design can expand the Pareto frontier of a ternary flip-flop in terms of energy consumption. We expect that the proposed ternary flip-flop will contribute to the development of energy-efficient sensor systems, such as ternary successive approximation register analog-to-digital converters.

An 8-bit Data Driving Circuit Design for High-Quality Images in Active Matrix OLEDs (고화질 Active Matrix OLED 디스플레이를 위한 8비트 데이터 구동 회로 설계)

  • Jo, Young-Jik;Lee, Ju-Sang;Yu, Sang-Dae
    • Proceedings of the KIEE Conference
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    • 2004.11c
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    • pp.632-634
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    • 2004
  • First for high-qualify images and reducing process-error and driving speed, the designed 8-bit data driving circuit consists of a constant transconductance bias circuit, D-F/Fs by shift registers using static transmission gates, 1st latch and 2nd latch by tristate inverters, level shifters, current steering segmented D/A converters by 4MSB thermometer decoder and 4LSB weighted type. Second, we designed gray amp for power saving. These data driving circuits are designed with $0.35-{\mu}m$ CMOS technologies at 3.3 V and 18 V power supplies and simulated with HSPICE.

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Dual-Mode Liquid Crystal Devices with Switchable Memory and Dynamic Modes

  • Yao, I-An;Kou, Hsiao-Ti;Yang, Chiu-Lien;Liao, Shih-Fu;Li, Jia-Hsin;Wu, Jin-Jei
    • Journal of Information Display
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    • v.10 no.4
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    • pp.184-187
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    • 2009
  • A liquid crystal device with switchable dynamic and memory modes was investigated and developed. The proposed device reveals the splay, $\pi$-twist, and bend states via selective switching among them. In the dynamic mode, the device is operated in the bend state, which exhibits a wide viewing-angle and a fast-response-time due to its self-compensated bend structure and flow-accelerated fast response time, respectively. In the memory mode, the permanent memory characteristics in the splay and $\pi$-twist sates are obtained, respectively. The switching mechanisms of the tristate device are also proposed.

Dual-Mode Liquid Crystal Devices with Switchable Memory and Dynamic Modes

  • Yao, I-An;Chen, Chueh-Ju;Yang, Chiu-Lien;Pang, Jia-Pang;Liao, Shih-Fu;Li, Jia-Hsin;Wu, Jin-Jie
    • 한국정보디스플레이학회:학술대회논문집
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    • 2009.10a
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    • pp.600-603
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    • 2009
  • The liquid crystal device with switchable dynamic mode and memory mode has been investigated and developed. The proposed device reveals splay, ${\pi}$ twist and bend states by selective switching among them. In the dynamic mode, this device is operated in the bend state which exhibits the wide view angle and fast response time properties due to the self-compensated bend structure and flow accelerated fast response time. In the memory mode, the permanent memory characteristics in the splay and ${\pi}$ twist sates are obtained, respectively. The switching mechanisms of the tristate device are also proposed.

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Microcomputer-based Data Acquisition System for the Measurements of Temperature and Weight in Food Processing (마이크로 컴퓨터를 이용한 식품가공(食品加工) 공정중(工程中)의 온도및 무게 측정용(測定用) Analog-digital 변환(變換)및 접속(接續) 시스템의 제작(製作))

  • Choi, Boo-Dol;Chun, Jae-Kun
    • Korean Journal of Food Science and Technology
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    • v.19 no.2
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    • pp.129-133
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    • 1987
  • To develop a microcomputer-based data acquisition system for measurement of variables such as temperature and weight in food process, a low-cost data acquisition system was developed using an Apple II microcomputer. The system consisted of a microcomputer, a temperature sensor made of pt-100, a strain gauge load cell for weighing, a preamplifier for signal conditionings and an interface device. Interface device was built with programmable interface chip MC 6821, tristate buffer 74244 and analog-to-digital converter ADC 0809. The analog signals of temperature and weight were serially acquisited upon the program. The BASIC language was used for operating the data acquisition and data handling programs. The system successfully measured the variables such as temperature and weight with various sampling intervals in food dehydration process.

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Implementation of an 8-Channel Statistical Multiplexer (8-채널 통계적 다중화기의 구현)

  • 이종락;조동호
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.21 no.5
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    • pp.79-89
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    • 1984
  • In this paper we present development of microprocessor-based 8-channel statistical multiplexer (SMUX). The hardware design includes one Z-80A CPU board with the clock rate of 4 MHz, one 16 Kbyte ROM board for program storage, one 16 Kbyte dynamic RAM board and three I/O boards, all connected through an S-100 compatible tristate bus. The SMUX can presently multiplex 8 channels with data rates ranging 50 bps to 9600 bps, but can be reduced to accommodate 4 channels by having a slight modification of software and removing one terminal I/O board. The system specifications meet CCITT recommendations X.25 link level, V.24, V.28, X.3 and X.28. Significant features of the SMUX are its capability of handling 4 input codes (ASCII, EBCDIC, Baudot, Transcode), the use of a dynamic buffer management algorithm, a diagnostic facility, and the efficient use of a single CPU for all system operation. Throughout the paper, detailed explanations are given as to how the hardware and software of the SMUX system have been designed efficiently.

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