• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.2
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• pp.99-104
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• 2020

In this study, we fabricated a metamorphic high-electron-mobility transistor (mHEMT) device with a T-type gate structure for the implementation of W-band monolithic microwave integrated circuits (MMICs) and investigated its characteristics. To fabricate the mHEMT device, a recess process for etching of its Schottky layer was applied before gate metal deposition, and an e-beam lithography using a triple photoresist film for the T-gate structure was employed. We measured DC and RF characteristics of the fabricated device to verify the characteristics that can be used in W-band MMIC design. The mHEMT device exhibited DC characteristics such as a drain current density of 747 mA/mm, maximum transconductance of 1.354 S/mm, and pinch-off voltage of -0.42 V. Concerning the frequency characteristics, the device showed a cutoff frequency of 215 GHz and maximum oscillation frequency of 260 GHz, which provide sufficient performance for W-band MMIC design and fabrication. In addition, active and passive modeling was performed and its accuracy was evaluated by comparing the measured results. The developed mHEMT and device models could be used for the fabrication of W-band MMICs.

• The Journal of Korean Medical History
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• v.18 no.2
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• pp.137-187
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• 2005

This thesis study of the medical concept Qiu Zheng Lu (求正錄) is discussed in the Lei Jing Fu Yi (類經附翼), a book authored by Zhang Jie Bin (張介賓) a medical doctor during the Chinese Ming (明) dynasty (1368-1683). The meaning of Qiu Zheng Lu (求正錄) is "searching for the rightness." In his book Zhang Jie Bin (張介賓) intended to clarify Qiu Zheng Lu (求正錄) by delineating the concept into four categories. These are: Sanjiao Baoluo Mingmen Bian (三焦包絡命門 辨) the theory of the triple warmer, the Pericardium, the Gate of Life ; Da Bao Lun (大寶論) the theory of the great treasure of the human body; Zhen Yin Lun (眞陰論) the theory of true-yin fluid; and Shi Er Zang Mai Hou Bu Wei Lun (十二臟脈候部位論) the theory of the part of the pulse and its condition in regards to the twelve viscera. Sanjiao Baoluo Mingmen Bian (三焦包絡命門辨), the theory of the triple warmer, the Pericardium, the Gate of Life. The triple warmer (三焦: Sanjiao) is composed of three parts: the upper, middle, and lower. This concept is also connected with the functions and roles of the vital organs. The upper burner is related to the heart and lungs. The middle burner is related to the liver and spleen. Whereas, the lower burner is related to the kidneys. Bao-Luo (包絡) is the Pericardium, the envelope of the heart, serving as the protector of the heart. Ming-Men (命門) is the Gate of Life, reffering to the vitals of life. It functions as kidney-yang which is considered as the origin of yang-energy of the human body, and serves partly as the function of cortico-adrenal gland in modern medicine. Zhang Jie Bin (張介賓) discussed the Da Bao Lun (大寶論) as the most important function in the human body because the Da Bao (大寶/great treasure) is the true-yang (眞陽) which is the affective force for physiological functions, and as the source of energy for life activities. Moreover, true-yang (眞陽) functions both as a heater and thermometer that warms the human body and indicates vitality by levels of body warmth respectively. The Zhen Yin Lun (眞陰論) theory states that if true-yang (眞陽) is energy, then true-yin (眞陰) is the source of energy. This can be likened to a tree with roots which absorbs nutrients from the ground (source), and spreads the nutrients (energy) through its branches. Thus, true-yin (眞陰) is the root cause for later functional activities of true-yang (眞陽). In Shi Er Zang Mai Hou Bu Wei Lun (十二臟脈候部位論) the theory of the pulse (脈 /Mai) and its condition in regards to the twelve viscera, Zhang Jie Bin (張介賓) insisted that when a diagnoses by the pulse is made the five vital organs and the six viscera (五臟六腑) of a human body should be harmoniously arranged in accordance with its respective part of the pulse. Furthermore, Zhang Jie Bin (張介賓) supported his theory with evidence from earlier Chinese medical doctors. And, by stating that human beings must cultivate and preserve their true-yin (眞陰) and true-yang (眞陽) energies he therefore created four new prescriptions called: Zuoguiyin (左歸飮), Youguiyin (右歸飮), Zuoguiwan (左 歸丸), Youguiwan (右歸丸). To further clarify his theory Zhang Jie Bin (張介賓) considered that the function of true-yang (眞陽) and true-yin (眞陰) is expressed by Ming-Men (命門). This theory is that for humans to be spiritually and physically healthy they must live in accord with natural law. Also, within the framework of natural law, astronomical and geographical factors must be considered for complete, holistic, health. Thus, Ming-Men is the basis for healthy living in the modern world.

• Proceedings of the KSR Conference
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• 2011.05a
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• pp.1195-1201
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• 2011

Since the release of safety standard IEC 61508 which defines functional safety of electronic safety-related systems, SIL(Safety Integrity Level) certification for railway systems has gained lots of attention lately. In this paper, we propose a new design technique of the computer board for train control systems with high reliability and safety. The board is designed with TMR(Triple Modular Redundancy) using a certified SIL3 Texas Instrument(TI)'s TMS570 MCU(Micro-Controller Unit) to guarantee safety and reliability. TMR for the control device is implemented on FPGA(Field Programmable Gate Array) which integrates a comparator, a CAN(Controller Area Network) communication module, built-in self-error checking, error discriminant function to improve the reliability of the board. Even if a malfunction of a processing module occurs, the safety control function based on the proposed technique lets the system operate properly by detecting and masking the malfunction. An RTOS (Real Time Operation System) called FreeRTOS is ported on the board so that reliable and stable operation and convenient software development can be provided.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1416-1417
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• 2011

킹크효과를 억제할 수 있는 새로운 f-모양 트리플게이트 구조를 가지는 다결정실리콘 박막트랜지스터는 추가적인 공정과정 없이 제안 및 제작되었다. 이러한 다결정실리콘 박막트랜지스터의 채널에는 순차적인 횡방향 고체화(Sequential Lateral Solidification, SLS)나 CW 레이져 횡방향 결정화(CW laser Lateral Crystallization, CLC) 등과 같은 방법으로 제작된 횡방향으로 성장시킨 그레인이 있다. 이 소자의 전체적인 전류흐름은 횡방향으로 성장시킨 그레인 경계에 강력하게 영향을 받는다. f-모양 트리플게이트에는 횡방향으로 성장시킨 그레인과 평행한 방향으로 위치한 채널, 그리고 수직인 방향으로 위치한 채널이 있다. 이 소자는 f-모양 게이트 구조에서의 비대칭 이동도를 이용하여 다결정실리콘 박막트랜지스터의 킹크효과를 효과적으로 억제시킬 수 있다는 사실을 실험과 시뮬레이션을 통해 검증되었다. 우리의 실험 결과는 이 논문에서 제안된 f-모양 트리플게이트 박막트랜지스터가 기존의 박막트랜지스터와 비교할 때 더 효과적으로 킹크 효과를 감소시킬 수 있다는 것을 보여주었다. 또한 고온 캐리어 스트레스 조건에서의 신뢰성도 개선할 수 있음이 확인되었다.

• Journal of the Optical Society of Korea
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• v.17 no.5
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• pp.362-370
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• 2013

In this paper, we propose a novel optical implementation of a 3DES algorithm based on dual XOR logic operations for a cryptographic system. In the schematic architecture, the optical 3DES system consists of dual XOR logic operations, where XOR logic operation is implemented by using a free-space interconnected optical logic gate method. The main point in the proposed 3DES method is to make a higher secure cryptosystem, which is acquired by encrypting an individual private key separately, and this encrypted private key is used to decrypt the plain text from the cipher text. Schematically, the proposed optical configuration of this cryptosystem can be used for the decryption process as well. The major advantage of this optical method is that vast 2-D data can be processed in parallel very quickly regardless of data size. The proposed scheme can be applied to watermark authentication and can also be applied to the OTP encryption if every different private key is created and used for encryption only once. When a security key has data of $512{\times}256$ pixels in size, our proposed method performs 2,048 DES blocks or 1,024 3DES blocks cipher in this paper. Besides, because the key length is equal to $512{\times}256$ bits, $2^{512{\times}256}$ attempts are required to find the correct key. Numerical simulations show the results to be carried out encryption and decryption successfully with the proposed 3DES algorithm.

• Journal of Electrical Engineering and information Science
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• v.2 no.5
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• pp.17-26
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• 1997

Interconnect characterization on a wafer level was performed. Test patterns for single, two-coupled, and triple-coupled lines ere designed by using 0.5$\mu\textrm{m}$ CMOS process. Then interconnect capacitances and resistances were experimentally extracted by using tow port network measurements, Particularly to eliminate parasitic effects, the Y-parameter de-embedding was performed with specially designed de-embedding patterns. Also, for the purpose of comparisons, capacitance matrices were calculated by using the existing CAD model and field-solver-based commercial simulator, METAL and MEDICI. This work experimentally verifies that existing CAD models or parameter extraction may have large deviation from real values. The signal transient simulation with the experimental data and other methodologies such as field-solver-based simulation and existing model was performed. as expected, the significantly affect on the signal delay and crosstalk. The signal delay due to interconnects dominates the sub-micron-based a gate delay (e.g., inverter). Particularly, coupling capacitance deviation is so large (about more than 45% in the worst case) that signal integrity cannot e guaranteed with the existing methodologies. The characterization methodologies of this paper can be very usefully employed for the signal integrity verification or he electrical design rule establishments of IC interconnects in the industry.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.751-754
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• 2000

When charge-trap SONOS cells are used flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM cells were fabricated using 0.35$\mu\textrm{m}$ standard memory cell embedded logic process including the ONO cell process. based on retrograde twin-well, single-poly, single metal CMOS process. The thickness of ONO triple-dielectric for memory cell is tunnel oxide of 24${\AA}$, nitride of 74 ${\AA}$, blocking oxide of 25 ${\AA}$, respectively. The program mode(Vg: 7,8,9 V, Vs/Vd: -3 V, Vb: floating) and the erase mode(Vg: -4,-5,-6 V, Vs/Vd: floating, Vb: 3V) by modified Fowler-Nordheim(MFN) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation($\Delta$Vth, S, Gm) characteristics than channel MFN tunneling operation. Also the program inhibit conditions of unselected cell for separated source lines NOR-tyupe flash memory application were investigated. we demonstrated that the program disturb phenomenon did not occur at source/drain voltage of 1 V∼4 V and gate voltage of 0 V∼4.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.38-47
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• 1999

We have designed a 16bit adder which reduces the power consumption at each level of architecture, logic and transistor. The conventional ELM adder has a major disadvantage which makes glitch in the G cell when the particular input bit patterns are applied, because of the block carry generation signal computed by the input bit pattern. Thus, we propose a low power adder architecture which can automatically transfer each block carry generation signal to the G cell of the last level to avoid glitches for particular input bit patterns at the architecture level. We also use a combination of logic styles which is suitable for low power consumption with static CMOS and low power XOR gate at the logic level. Futhermore, The variable-sized cells are used for reduction of power consumption according to the logic depth of the bit propagation at the transistor level. As a result of HSPICE simulation with $0.6\mu\textrm{m}$ single-poly triple-metal LG CMOS standard process parameter, the proposed adder is superior to the conventional ELM architecture with fixed-sized cell and fully static CMOS by 23.6% in power consumption, 22.6% in power-delay-product, respectively.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.6
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• pp.109-118
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• 1998

This paper presents an ASIC implementation of video encoder which converts either digital RGB or YCbCr to S-video(Y/C) and composite video signal. The video timing signal of this encoder includes horizontal sync., vertical sync. signal and blanking, and this encoder supports field identification signal which is convenient for video editing. The encoder has been designed in the 4 stages pipeline structure to assure the stable operation of each submodule. The proposed encoder requires only 20K gates ,which is a 40% reduction in hardware compared with [13]. The designed encoder was fabricated in $0.65{\mu}m$ SOG triple metal CMOS technology. Chip size is $3.7478mm {\times} 4.4678mm$ including PAD, gate counts is 19,468 and dissipated power is 0.9W.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.10A
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• pp.1546-1554
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• 1999

In this paper, Dynamic Fault Tree algorithm(DFT algorithm) is presented. This algorithm provides a concise representation of dynamic fault tolerance system including fault recovery techniques with fault detection, mask and switching function. And this algorithm define FDEP, CSP, SEQ, PAG gate which captures the dynamic characteristics of system. It show that this algorithm solved the constraints to satisfy the dynamic characteristics of system which there are in Markov and also this is able to satisfy the dynamic characteristics of system which there are in Markov and also this is able to covered the disadvantage of Fault tree methods. To show the key advantage of this algorithm, a traditional method, that is, Markov and Fault Tree, applies to TMR and Dual-Duplex systems with the dynamic characteristic and a presented method applies to those. He results proved that the DFT algorithm for solving the problems of the system is more effective than the Markov and Fault tree analysis model..