• Journal of the Korean Institute of Telematics and Electronics
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• v.8 no.6
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• pp.8-16
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• 1971

This paper describes the transistorized linear counting ratemeter which can be uses to indicate on the meter or record the counting rates of the nuclear radiations produced from the atomic reactor or from the radio isotopes. Tte feature of this ratemeter is the use of the transistor chopper for good stabilization. At the input stage of the a. c. amplifier a composite emitter follower buffer stage has been used to give the high input impedance. A hybrid parameter equivalent circuit was modeled for the analysis of this buffer stage. The counting rates can be linearly measured from few CPS up to 100KCPS in 4 ranges. The resolution is less than 0.5$\mu$sec and the output drift at the room temperature with 7-hour continuous operation is in the order of $\pm$0.5$\mu$A.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.2
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• pp.187-195
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• 1999

A series feedback DRO operating at 3.2 GHz applicable to the spectrum analyzer as the second local oscillator, is designed and fabricated. We can obtain a low noise by utilizing the small signal S-parameter of the transistor and adjusting the reflection coefficient from the coupling coefficient between dielectric resonator and microstrip line. The results show that output power is 10.50 dBm, a stable low phase noise is -116 dBc/Hz at a 10 kHz offset frequency and a harmonic characteristic is 19.33 dBc.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.1
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• pp.1-11
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• 2000

An accurate technique to retrieve HEMT modeling parameters with measurements of S-parameters and DC characteristics of HEMT is proposed. The extrinsic series resistances among HEMT modeling parameters are determined by the FUKUI method using the measured DC characteristics. And other parameters are determined by the measured S-parameters by HP 8510C Network Analyzer with various values of DC bias. The transconductance retrieved from the measured S-parameters, however, shows only 0.078% error comparing with the measured gm values. Therefore, the S-parameters measured directly for an individual transistor should be used for an accurate determination of the model parameters. The procedure for the retrieval of the circuit modeling parameters redescribed in detail in this thesis.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.143-143
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• 2009

본 논문은 2500V급 planar type의 NPT(Nun-Punch Through)형 IGBT설계 및 제작에 앞서 IGBT(Insulated Gate Bipolar Transistor)소자가 갖는 구조적 변수가 전기적 특성 (Breakdown Voltage, Turnoff Time, Saturation Voltage, 등)결과에 미치는 영향을 분석하여 IGBT 소자가 갖는 구조적 손실을 최적화 하는데 목표를 두었다. 최적화의 진행은 공정 시뮬레이터인 Tsuprem4와 디바이스 분석 시뮬레이터인 MEDICI를 이용하여 소자가 갖는 각각의 parameter값이 전기적 특성에 미치는 영향을 분석함으로 진행 되어졌으며, 향후 고속철 등과 같은 대용량 산업에 기여할 것으로 판단된다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.5-8
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• 1998

기존의 바이폴라 논리회로에서 신호변환시 베이스 영역의 소수 캐리어를 빨리 제거 하기 위해서, 베이스 부분의 매몰충을 줄여서 npn트랜지스터의 베이스와 에피충과 기판사이에 병합 pnp 트랜지스터를 생성한 트랜지스터와 게이트 당 전달 지연 시간을 측정하기 위한 링-발진기를 설계, 제작하였다. 게이트의 구조는 수직 npn 트랜지스터와 기판과 병합 pnp 트랜지스터이다. 소자 시뮬레이션의 자료를 얻기 위하여 수직 npn 트랜지스터와 병합 pnp 트랜지스터의 전류-전압 특성을 분석하여 특성 파라미터를 추출하였다. 결과로서 npn 트랜지스터의 에미터의 면적이 기존의 접합넓이에 비해서 상당히 적기 때문에 에미터에서 진성베이스로 유입되는 캐리어와 가장자리 부분으로 유입되는 캐리어가 상대적으로 많기 때문에 이 많은 양은 결국 베이스의 전류가 많이 형성되며, 또 콜렉터의 매몰층이 거의 반으로 줄었기 때문에 콜렉터 전류가 적게 형성되어 이득이 낮아진다. 병합 pnp 트랜지스터는 베이스폭이 크고 농도 분포에서 에미터의 농도와 베이스의 농도 차이가 적기 때문에 전류 이득이 낮아졌다. 게이트를 연결하여 링-발진기를 제작하여 측정한 AC특성의 출력은 정현파로 논리전압의 진폭은 200mV, 최소 전달 지연시간은 211nS이며, 게이트당 최소 전달지연 시간은 7.26nS의 개선된 속도 특성을 얻었다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.1
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• pp.93-102
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• 1994

This paper, presents SECRET(SEC REliability Tool), which predicts reliability problems related to the hot-carrier and electromigration effects on the submicron MOSFETs and interconnections. To simulate DC and AC lifetime for hot-carrier damaged devices, we have developed an accurate substrate current model with the geometric sensitivity, which has been verified over the wide ranges of transistor geometries. A guideline can be provided to design hot-carrier resistant circuits by the analysis of HOREL(HOT-carrier RFsistant Logic) effect, and circuit degradation with respect to physical parameter degradation such as the threshold voltage and the mobility can also be expected. In SECRET, DC and AC MTTF values of metal lines are calculated based on lossy transmission line analysis, and parasitic resistances, inductances and capacitances of metal lines are accurately considered when they operate in the condition of high speed. Also, circuit-level reliability simulation can be applied to the determination of metal line width and-that of optimal capacitor size in substrate bias generation circuit. Experimental results obtained from the several real circuits show that SECERT is very useful to estimate and analyze reliability problems.

• Transactions on Electrical and Electronic Materials
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• v.5 no.4
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• pp.129-132
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• 2004

The electrothermal characteristics of a high voltage LIGBT(Lateral Insulated Gate Bipolar Transistor) using thin silicon on insulator (SOI) and silicon on sapphire (SOS) such as thermal conductivity and sink is analyzed by MEDICI. The device simulations demonstrate that the thermal conductivity of the buried oxide is an important parameter for modeling of the thermal behavior of SOI devices. In this paper we simulated the thermal conductivity and temperature distribution of a SOI LIGBT with an insulator layer of SiO$_2$ and $Al_2$O$_3$ at before and after latch-up and verified that the SOI LIGBT with the $Al_2$O$_3$ insulator had good thermal conductivity and reliability.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.5-5
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• 2010

Gallium Nitride(GaN)는 LED, Laser 등에 사용되는 광학적 특성뿐만 아니라 Wide Bandgap의 전기적 특성 또한 주목받고 있다. 본 논문은 600V급 GaN(Gallium Nitride) Power SIT(Static Induction Transistor)에 대해서 Design Parameter 변환에 따른 전기적 (Breakdown Voltgage, On-state Voltage Drop)특성과 열적 (Lattice Temperature Distribution)특성변화를 분석하여 소자가 갖는 구조적 손실을 최소화하였다. 또한, 기존 실리콘 기반 전력소자와 특성 비교를 통하여 GaN Power SIT의 우수성을 증명하였다. GaN Power SIT 소자 설계 및 최적화를 위해서 Silvaco사의 소자 시뮬레이터인 ATLAS를 사용하였다. 실험 결과 수 ${\mu}m$의 소자 두께만으로도 실리콘 전력소자에 비해 더 뛰어난 열 특성과 더 적은 전력소모를 갖는 600V급 GaN Power SIT 소자를 구현할 수 있었다.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.212-215
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• 1999

High-speed device is essential to optoelectric IC for optical storage system such as CD-ROM, DVD, and to ADC for high-speed communication system. This paper represents the BiCMOS process which contains high-speed SAVEN bipolar transistor and analyzes the frequency and switching characteristics of it briefly. Finally, to prove that the SAVEN device is adequate for high-speed system, latched comparator operating at 500MHz is designed with the SPICE parameter extracted from BiCMOS device simulation.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.8
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• pp.33-41
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• 1998

We have designed a high speed and low power 16bit-ELM adder with variable-sized cells uitlizing the fact that the logic depth of lower bit position is less than that of the higher bit position int he conventional ELM architecture. As a result of HSPICE simulation with 0.8.mu.m single-poly double-metal LG CMOS process parameter, out 16bit-ELM adder with variable-sized cells shows the reduction of power-delay-product, which is less than that of the conventional 16bit-ELM adder with reference-sized cells by 19.3%. We optimized the desin with various logic styles including static CMOs, pass-transistor logic and Wang's XOR/XNOR gate. Maximum delay path of an ELM adder depends on the implementation method of S cells and their logic style.