• Journal of Korea Society of Industrial Information Systems
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• v.6 no.3
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• pp.123-127
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• 2001

The prediction method of the parameter C/sub gs/ of CMOS transistor is proposed by calculating the mobil charge in inversion layer of COMS transistor. This parameter C/sub gs/ decided on the cutoff frequency in MOS transistor in RF range and coupled input and output. This parameter C/sub gs/ in RF range is very important parameter in small signal circuit model. This proposed method is contributed to developing software of extracting parameter value in equivalent circuit model. The method provide the important information to construct a RF nonlinear model for multifinger gate MOSFET. This method will be very valuable to develop a large signal MOSFET model for nonlinear RF IC design.

• Proceedings of the KAIS Fall Conference
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• 2003.06a
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• pp.253-255
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• 2003

Flash memory는 device 특성상 peripheral circuit을 구성하는 transistor의 종류가 다양하고, 이에 따른 각 transistor의 동작 전압 영역이 넓다. 이에 따라 설계 초기의 전기적 특성 스펙 절정을 위해서는, silicon 상에서 소자의 scale down에 따른 전기적 특성을 선 검증하는 과정이 필수적이었으며, 이로 인해 설계 및 소자 개발의 기간을 단축하기 어려웠다. 본 연구에서는 TCAD tool을 사용하여 silicon상에서의 제작 공정을 거치지 않고, 효과적으로 model parameter를 생성할 수 있도록 하는 방법을 제안하여. 전기적 특성 스펙 결정과 설계 단계의 시간 지연을 감소할 수 있도록 한다.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.49-52
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• 2002

A new method is developed to extract model parameters of SiGe HBT equivalent circuit including the base impedance and base-collector junction capacitance. Using this method, all resistances and capacitances of SiGe HBT are independently determined from measured S-parameters using two-port parameter formula. This method is proposed to reduce possible errors generated from global optimization process, and its accuracy has been verified by finding good agreements between measured and modeled current / power gain up to 18 GHz.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.382-383
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• 2013

Gate-controlled spin-orbit interaction parameter is a key factor for developing spin-Field Effect Transistor (Spin-FET) in a quantum well structure because the strength of the spin-orbit interaction parameter decides the spin precession angle [1]. Many researches show the control of spin-orbit interaction parameter in n-type quantum channels, however, for the complementary logic device p-type quantum channel should be also necessary. We have calculated the spin-orbit interaction parameter and the effective mass using the Shubnikov-de Haas (SdH) oscillation measurement in a GaSb two-dimensional hole gas (2DHG) structure as shown in Fig 1. The inset illustrates the device geometry. The spin-orbit interaction parameter of $1.71{\times}10^{11}$ eVm and effective mass of 0.98 $m^0$ are obtained at T=1.8 K, respectively. Fig. 2 shows the gate dependence of the spin-orbit interaction parameter and the hole concentration at 1.8 K, which indicates the spin-orbit interaction parameter increases with the carrier concentration in p-type channel. On the order hand, opposite gate dependence was found in n-type channel [1,2]. Therefore, the combined device of p- and n-type channel spin transistor would be a good candidate for the complimentary logic device.

• 전기의세계
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• v.11
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• pp.8-13
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• 1963

Solid state nuclear radiation detector에 사용되는 transistor에 의한 저잡음 charge sensitive preamplifier의 설계방식과 이에 대한 실측결과에 관하여 기술하였다. 먼저 transistor noise의 제원인을 분석하고 이 잡음들을 최소로 하기 위하여 이에 관련된 각 parameter에 대하여 이론 및 실험적으로 고찰하였다. 지금까지 알려진 진공관식 증폭기의 최소잡음은 등가전자수로 표시하면 약 250전자 정도이고 그 transistor증폭기에 있어서는 약 1,000전자 정도이었으나 본 설계방식에 의하여 제작된 transistor증폭기에서는 detector를 포함한 전 input capacitance가 약 100PF일때 약 400전자의 양호한 저잡음특성을 보이고 있으며 linearity 및 stability도 매우 좋은 결과를 보이고 있다. 여기에 사용된 cascode회로 자체는 이미 오래 전부터 알려져 있었지만 잡음을 최소로 하기 위한 설계방법은 지금껏 알려지지 않고 있으므로 본 논문에서는 전치증복기의 소요이득에서 잡음을 최소로 할 수 있는 설계방식을 확립하여 이 방식에 의한 실측결과는 종래의 transistor를 사용한 것보다 가장 좋았다.

• ETRI Journal
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• v.31 no.5
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• pp.604-606
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• 2009

The primary dose effects on an insulated gate bipolar transistor (IGBT) irradiated with a $^{60}Co$ gamma-ray source are found in both of the components of the threshold shifting due to oxide charge trapping in the MOS and the reduction of current gain in the bipolar transistor. In this letter, the IGBT macro-model incorporating irradiation is implemented, and the electrical characteristics are analyzed by SPICE simulation and experiments. In addition, the collector current characteristics as a function of gate emitter voltage, VGE, are compared with the model considering the radiation damage of different doses under positive biases.

• Journal of the Korean Institute of Telematics and Electronics
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• v.15 no.3
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• pp.7-10
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• 1978

A method of full wave rectification is proposed which is accomplished by an inverter circuit including R-feed back. Both halves of the input cycle can be presented in the out put by composing a conductive half cycle and an inactive half cycle substituted by feed back in the cut off state.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.70-70
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• 2009

In this paper, we proposed 2500V Non punch-through(NPT) Insulated gate bipolar transistor(IGBT) for high voltage industry application. we carried out optimal simulation for high efficiency of 2500V NPT IGBT according to size of device. In results, we obtaind design parameter with 375um n-drift thickness, 15um gate length, and 8um emitter windows. After we simulate with optimal parameter, we obtained 2840V breakdown voltage and 3.4V Vce,sat. These design and process parameter will be used designing of more 2000V NPT IGBT devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.4
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• pp.273-279
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• 2010

In this paper, we proposed 2500 V Non punch-through(NPT) Insulated gate bipolar transistor(IGBT) for high voltage industry application. we carried out optimal simulation for high efficiency of 2500 V NPT IGBT according to size of device. In results, we obtaind design parameter with 375 um n-drift thickness, 15 um gate length, and 8um emitter windows. After we simulate with optimal parameter, we obtained 2840 V breakdown voltage and 3.4V Vce,sat. These design and process parameter will be used designing of more 2000 V NPT IGBT devices.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.4 no.3
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• pp.177-182
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• 2003

In the case of the flash memory, various kinds of transistors and the wide range of operation voltage are necessary to achieve the read/write operations. Therefore, the characteristics of transistors are measured in the silicon for the circuit design, and the test vehicle run must be processed. In this study, an efficient design flow is suggested using TCAD tools. The test vehicle is replaced with well-calibrated TCAD simulation. First, the calibration methodology is introduced and tested for flash memory device. The calibration errors are less than 5% of a full chip operation, which is accepted by the designers. The results of the calibration were used to predict I-V curves and model parameter of the various transistors for the design of flash device.