• Journal of Korean Institute of Industrial Engineers
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• v.31 no.1
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• pp.36-43
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• 2005

It is the basic requirement of design process of parts assembly to specify geometric dimensions and tolerances of product characteristics. Among them, tolerance stack analysis is one of the important methods to specify tolerance zone. Tolerance stack analysis is to calculate gap using tolerances which includes geometric and coordinate dimensions. In this study, we suggested more general method called the virtual method to analyze tolerance stack. In virtual method, tolerance zone is formed by combination of dimensional tolerance, geometric tolerance and bonus tolerance. Also tolerance zone is classified by virtual boundary condition and resultant boundary condition. So gap can be defined by combination of virtual boundary and/or resultant boundary. Several examples are used to show the effectiveness of new method comparing to other methods.

• Proceedings of the Safety Management and Science Conference
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• 2002.05a
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• pp.99-103
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• 2002

It is the basic requirement of product characteristics to specify geometric dimensions and tolerances during design process of parts assembly. Therefore, there are many tolerance stack analysis method to explain tolerance zone. Tolerance stack analysis is to calculate gap using tolerances which includes geometric and coordinate dimension. In this study, we compared several different stack analysis method and try to suggest more general method called the Virtual Method to analyze tolerance stack.

• Journal of Korean Society for Quality Management
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• v.22 no.4
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• pp.79-101
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• 1994

In modern manufacturing, a product consists of many components created by different processes. Variations in the individual component dimensions and in the processes may result in unacceptable final assemblies. Thus, engineers have increased pressure to properly set tolerance specifications for individual components and to control manufacturing processes. When a proper variation stack-up analysis is not performed for all of the components in a functional system, all component parts can be within specifications, but the final assembly may not be functional. Thus, in order to improve the performance of the final assembly, a proper variation stack-up analysis is essential for specifying dimensional tolerances and process control. This research provides a detailed case example of the use of variation stack-up analysis using a Monte Carlo simulation method to improve the defect rate of a complex process, which is the commutator brush track undercut process of an armature assembly of a small motor. Variations in individual component dimensions and process mean shifts cause high defect rate, Since some dimensional characteristics have non-normal distributions and the stack-up function is non-linear, the Monte Carlo simulation method is used.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.5
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• pp.259-265
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• 2016

In this paper, we present an architecture for the fault isolation by applying virtualization-based multi-stack technologies. We propose the simultaneous sharing and switching mechanism using virtualied serial communications. Each guest OS has its own virtual serial device. The distribution module provides communications between the guest OS's through the virtual serial devices and simultaneously detect the liveness of the guest OS. The suggested mechanism has been implemented in VirtualBox and shows satisfactory performance in transmission speed and data sharing capability with virtual RS232.

• Korean Journal of Computational Design and Engineering
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• v.17 no.6
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• pp.398-408
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• 2012

This paper investigates the tolerance stack-up in a commercial sliding-type mobile phone model developed by a Korean electronics company, with focus on the dimensional quality of the gap between the sliding top and the main body. The tolerance analysis in this study is done using a commercial software package, which runs Monte Carlo simulations to produce the statistical distributions of the gap size at desired locations. Such an analysis revealed that the original design did not yield the desired dimensional quality of the gap. Through a series of systematic analyses and syntheses, an improved design is proposed for the nominal dimensions and tolerances of selected features of the parts. The proposed design was validated, through tolerance analysis simulation, to meet the desired requirement of the gap quality.

• Journal of IKEEE
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• v.23 no.1
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• pp.338-341
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• 2019

In this paper, we propose a novel ESD device with improved characteristics of LVTSCR, which is a representative ESD protection device, and verify the N-stack technology for design optimized for each required voltage of a specific application. The characteristics of the holding voltage and the trigger voltage, which are the main parameters, are examined and the temperature characteristic, which is an indicator of the tolerance characteristic, is also verified. well region and a parasitic NPN to form a series-connected structure. We used synopsys' T-cad simulation tool for characterization.

• Journal of IKEEE
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• v.21 no.3
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• pp.234-239
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• 2017

In this paper, we propose an ESD (Electrostatic Discharge) protection circuit based on a new structure of SCR (Silicon Controlled Rectifier) embedded with PMOS structure. The proposed ESD protection circuit has a built-in PMOS structure and has a latch-up immunity characteristic and an improved tolerance characteristic. To verify the characteristics of the proposed ESD protection circuit and to analyze its operating characteristics, we compared and analyzed the characteristics of the existing ESD protection circuit using TCAD simulation. Simulation results show that the proposed protection ESD protection circuit has superior latch-up immunity characteristics like the existing SCR-based ESD protection device HHVSCR (High Holding Voltage SCR). Also, according to the results of the HBM (Human Body Model) maximum temperature test, the proposed ESD protection circuit has a maximum temperature value of 355K, which is about 20K lower than the existing HHVSCR 373K. In addition, the proposed ESD protection circuit with improved electrical characteristics is designed by applying N-STACK technology. As a result of the simulation, the proposed ESD protection circuit has a holding voltage characteristic of 2.5V in a single structure, and the holding voltage increased to 2-STACK 4.2V, 3-STACK 6.3V, 4-STACK 9.1V.

• Journal of Hydrogen and New Energy
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• v.18 no.4
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• pp.439-445
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• 2007

Proton exchange membrane Fuel Cells(PEMFCs) have been spotlighted because of their broad potential application for potable electrical devices, automobiles and residential usages. However, their utilization is limited to low temperature operation due to the electrolyte dehydration at high temperature. High temperature PEMFC operation offers high CO tolerance and easy water management. This review presents development of high temperature($120{\sim}200^{\circ}C$) PEMFC. Especially, PEMFC which is based on acid-doped PBI membrane is discussed.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04a
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• pp.381-384
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• 2002

This paper describes the motivation, design and performance of bi-active Load balancer in Linux Virtual Server. The goal of bi-active Load balancer is to provide a framework to build highly scalable, fault-tolerant services using a large cluster of commodity servers. The TCP/IP stack of Linux Kernel is extended to support three IP load balancing techniques, which can make parallel services of different kinds of server clusters to appear as a service on a single IP address. Scalability is achieved by transparently adding or removing a node in the cluster. and high availability is provided by detecting node or daemon failures and reconfiguring the system appropriately. Extensive simulation reveals that the proposed approach improves the reply rate about 20% compared to earlier design.

• Journal of Information Processing Systems
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• v.18 no.6
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• pp.741-754
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• 2022

Openstack is widely used as a representative open-source infrastructure of the service (IaaS) platform. The Openstack Identity Service is a centralized approach component based on the token including the Memcached for cache, which is the in-memory key-value store. Token validation requests are concentrated on the centralized server as the number of differently encrypted tokens increases. This paper proposes the practical Byzantine fault tolerance (PBFT) blockchain-based Openstack Identity Service, which can improve the performance efficiency and reduce security vulnerabilities through a PBFT blockchain framework-based decentralized approach. The experiment conducted by using the Apache JMeter demonstrated that latency was improved by more than 33.99% and 72.57% in the PBFT blockchain-based Openstack Identity Service, compared to the Openstack Identity Service, for 500 and 1,000 differently encrypted tokens, respectively.