• Journal of the Korea Institute of Information Security & Cryptology
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• v.28 no.3
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• pp.545-550
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• 2018

Ultra-lightweight block cipher CHAM, consisting of simple addition, rotation, and eXclusive-or operations, enables the efficient implementations over both low-end and high-end Internet of Things (IoT) platforms. In particular, the CHAM block cipher targets the enhanced computational performance for the low-end IoT platforms. In this paper, we introduce the efficient implementation techniques to minimize the memory consumption and optimize the execution timing over 8-bit AVR IoT platforms. To achieve the higher performance, we exploit the partly iterated expression and arrange the memory alignment. Furthermore, we exploit the optimal number of register and data update. Finally, we achieve the high RANK parameters including 29.9, 18.0, and 13.4 for CHAM 64/128, 128/128, and 128/256, respectively. These are the best implementation results in existing block ciphers.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.1
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• pp.128-136
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• 2008

In this paper, we propose a new cache structure for effective error correction of soft error. We added check bit and SEEB(soft error evaluation block) to evaluate the status of cache line. The SEEB stores result of parity check into the two-bit shit register and set the check bit to '1' when parity check fails twice in the same cache line. In this case the line where parity check fails twice is treated as a vulnerable to soft error. When the data is filled into the cache, the new replacement algorithm is suggested that it can only use the valid block determined by SEEB. This structure prohibits the vulnerable line from being used and contributes to efficient use of cache by the reuse of line where parity check fails only once can be reused. We tried to minimize the side effect of the proposed cache and the experimental results, using SPEC2000 benchmark, showed 3% degradation in hit rate, 15% timing overhead because of parity logic and 2.7% area overhead. But it can be considered as trivial for SEEB because almost tolerant design inevitably adopt this parity method even if there are some overhead. And if only parity logic is used then it can have $5%{\sim}10%$ advantage than ECC logic. By using this proposed cache, the system will be protected from the threat of soft error in cache and the hit rate can be maintained to the level without soft error in the cache.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.7
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• pp.273-281
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• 2003

This paper proposes a new time synchronization scheme for the Automatic Identification System(AIS). The proposed scheme utilizes a Temperature Compensated Crystal Oscillator(TCXO) as a local reference clock, and consists of a Digitally Controlled Oscillator(DCO), a divider, a phase comparator, and register blocks. Primary time reference is IPPS from GPS receiver that is synchronized to Universal Time Coordinated(UTC). And if GPS is unavailable, other station's signal is utilized as secondary time reference. The phase comparator measures time difference between the 1PPS and the generated transmit clock. The measured time difference is compensated by controlling the DCO and the transmit clock is synchronized to the Universal Time Coordinated(UTC). The synchronized transmit clock(9600Hz) is divided into the transmitting time slot(37.5Hz). The proposed scheme is tested in an experimental AIS transponder set. The experimental result shows that the proposed module satisfies the timing specification of the AIS technical standard, ITU-R M.1371-1.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.1
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• pp.26-35
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• 2005

Generally, we employ FSMs for the design of controllers in digital systems. FSMs are Implemented with state diagrams generated from control flow. With HDL, we design and verify FSMs based on state diagrams. As the number of states in the system increases, the verification or modification processes become complicated, error prone and time consuming. In this paper, we propose a control flow oriented hardware description language at the register transfer level called Cycle-C. Cycle-C describes FSMs with timing information and control How intensive algorithms. The Cycle-C description is automatically converted into FSMs in the form of synthesizable RTL VHDL. In experiments, we design FSMs for control intensive interface circuits. There is little area difference between Cycle-C design and manual design. In addition, Cycle-C design needs only 10~50% of the number lines of manual RTL VHDL designs.

• Journal of IKEEE
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• v.23 no.3
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• pp.800-804
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• 2019

This paper presents a dual-loop sub-sampling digital PLL for a 2.4 GHz IoT applications. The PLL initially performs a divider-based coarse lock and switches to a divider-less fine sub-sampling lock. It achieves a low in-band phase noise performance by enabling the use of a high resolution time-to-digital converter (TDC) and a digital-to-time converter (DTC) in a selected timing range. To remove the difference between the phase offsets of the coarse and fine loops, a phase offset calibration scheme is proposed. The phase offset of the fine loop is estimated during the coarse lock and reflected in the coarse lock process, resulting in a smooth transition to the fine lock with a stable fast settling. The proposed digital PLL is designed by SystemVerilog modeling and Verilog-HDL and fully verified with simulations.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.3
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• pp.23-32
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• 2001

Since the LILI-128 cipher is a clock-controlled keystream generator, the speed of the keystream data is degraded in a clock-synchronized hardware logic design. Basically, the clock-controlled $LFSR_d$ in the LILI-128 cipher requires a system clock that is 1 ~4 times higher. Therefore, if the same clock is selected, the system throughput of the data rate will be lowered. Accordingly, this paper proposes a 4-bit parallel $LFSR_d$, where each register bit includes four variable data routines for feed feedback of shifting within the $LFSR_d$ . Furthermore, the timing of the propose design is simulated using a $Max^+$plus II from the ALTERA Co., the logic circuit is implemented for an FPGA device (EPF10K20RC240-3), and the throughput stability is analyzed up to a late of 50 Mbps with a 50MHz system clock. (That is higher than the 73 late at 45 Mbps, plus the maximum delay routine in the proposed design was below 20ns.) Finally, we translate/simulate our FPGA/VHDL design to the Lucent ASIC device( LV160C, 0.13 $\mu\textrm{m}$ CMOS & 1.5v technology), and it could achieve a throughput of about 500 Mbps with a 0.13$\mu\textrm{m}$ semiconductor for the maximum path delay below 1.8ns.