• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.7
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• pp.545-551
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• 2013

Timing recovery loop composed of the Timing Error Detector(TED), loop filter and resampler is widely used for the timing synchronization in MQASK receivers. Since TED is sensitive to the delay between the symbol period of the signal and sampling period, the output is averaged out when the symbol rate and sampling rate are quite different the recovery loop cannot work at all. This paper presents a sampling frequency discriminator (SRD), which detects the frequency offset of the sampling clock to the symbol clock of the MQASK data transmitted. Employing the SRD, the closed loop timing recovery scheme performs the frequency-aided timing acquisition and achieve the synchronization at extremely high sampling frequency offset, which can be used in variable symbol rate MQASK receivers.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.9C
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• pp.905-912
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• 2007

This paper proposes an efficient estimation and compensation scheme of IQ imbalance for OFDM-based WLAN systems in the presence of symbol timing error. Since the conventional scheme assumes perfect time synchronization, the criterion of the scheme used to derive the estimation of IQ imbalance is inadequate in the presence of the symbol timing error and the system performance is seriously degraded. New criterion and compensation scheme considering the effect of symbol timing error are proposed. With the proposed scheme, the IQ imbalance can be almost perfectly eliminated in the presence of symbol timing error. The bit error rate performance of the proposed scheme is evaluated by the simulation. In case of 54 Mbps transmission mode in IEEE 802.11a system, the proposed scheme achieves a SNR gain of 4.3dB at $BER=2{\cdot}10^{-3}$. The proposed compensation algorithm of IQ imbalance is implemented using Verilog HDL and verified. The proposed IQ imbalance compensator is composed of 74K logic gates and 6K bits memory from the synthesis result using 0.18um CMOS technology.

• Transactions of the KSME C: Technology and Education
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• v.3 no.2
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• pp.89-96
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• 2015

Based on multi-body dynamic software RecurDyn, this paper proposes a modified form of timing silent chain system combing with the existing problem that vibration and chain tension is too large, which is applied for complicated conditions in a V-type engine, such as high speed, variable loads. The analysis of chain drive meshing characteristics is completed. Using the multi-body dynamic soft-ware RecurDyn, the dynamics characteristics of the improved system is studied, including chain tension, transmission error, chain fluctuations, equivalent spring force in different operating conditions. The study results show that chain tension, transmission error, chain fluctuation and equivalent spring force are within the scope of permission, all of them can meet the design requirement. There-fore, the design of this system is reasonable and practicable. The research results will provide a basis for assessing timing silent chain system in a V-type engine and a theoretical reference for designing and optimizing the timing silent chain system.

• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.4
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• pp.55-60
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• 1983

A new type of digital phase-locked loop (DPLL) that employs a multilevel quantified timing error detector (TED) is proposed and analyzed under the assumption of negligible quantizing effect and no noise. Since the timing error is quantized uniformly, the TED has a linear characteristic. From the linear characteristic of TED, a first order difference equation describing the behavior of the loop is derived. Using the system equation, the loop is analyzed mathematically for phase step and frequency step input. Desired locking condition for the loop to be locked and the lock range for the DPLL's to achieve exact locking independently of initial conditions are ob-tained. And these analyses are confirmed by timing error plane plots and computer simulation.

• Journal of Broadcast Engineering
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• v.16 no.1
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• pp.85-95
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• 2011

In this paper, we propose an alternative carrier phase independent timing recovery method for VSB receivers. The Gardner algorithm may not estimate a timing offset in VSB systems when the residual carrier phase offset is contained in the signal. We use the conjugate multiplication of received signals for cancelling out the carrier phase offset. Then Gardner algorithm is employed for extracting the spectral line. The proposed method generates a consistent timing error even in the presence of the carrier phase offset.

• Journal of the Korea Institute of Military Science and Technology
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• v.13 no.3
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• pp.453-460
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• 2010

For high quality image acquisition, compensating air-vehicle motion is essential for airborne SAR system. This paper describes a timing control based motion compensation method for airborne SAR system. Efficient timing control is critical for SAR system since it maintains many timing signals and timing setting for the signals should be updated frequently. This paper proposes Timing Cluster method as an efficient means for timing control of SAR system. Moreover, this paper suggests a simple and efficient method to compensate air-vehicle motion based on the Timing Cluster method. Timing Cluster method enables SAR system to control the timing in a timing noncritical way just maintaining little amount of information.

• ETRI Journal
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• v.29 no.5
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• pp.596-606
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• 2007

It is well known that an OFDM receiver is vulnerable to synchronization errors. Despite fine estimations used in the initial acquisition, there are still residual synchronization errors. Though these errors are very small, they severely degrade the bit error rate (BER) performance. In this paper, we propose a residual error elimination scheme for the digital OFDM baseband receiver aiming to improve the overall BER performance. Three improvements on existing schemes are made: a pilot-aided recursive algorithm for joint estimation of the residual carrier frequency and sampling time offsets; a delay-based timing error correction technique, which smoothly adjusts the incoming data stream without resampling disturbance; and a decision-directed channel gain update algorithm based on recursive least-squares criterion, which offers faster convergence and smaller error than the least-mean-squares algorithms. Simulation results show that the proposed scheme works well in the multipath channel, and its performance is close to that of an OFDM system with perfect synchronization parameters.

• Journal of information and communication convergence engineering
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• v.19 no.1
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• pp.22-28
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• 2021

Convolutional neural networks (CNNs) are one of the most frequently used artificial intelligence techniques. Among CNN-based applications, small and timing-sensitive applications have emerged, which must be reliable to prevent severe accidents. However, as the small and timing-sensitive systems do not have sufficient system resources, they do not possess proper error protection schemes. In this paper, we propose MATE, which is a low-cost CNN weight error correction technique. Based on the observation that all mantissa bits are not closely related to the accuracy, MATE replaces some mantissa bits in the weight with error correction codes. Therefore, MATE can provide high data protection without requiring additional memory space or modifying the memory architecture. The experimental results demonstrate that MATE retains nearly the same accuracy as the ideal error-free case on erroneous DRAM and has approximately 60% accuracy, even with extremely high bit error rates.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.4
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• pp.37-42
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• 1984

In this paper, effective methods of symbol timing in a 9600 bps modem are presented. The symbol timing circuit consists of a square-low device followed by a high-Q narrow band-pass filter tuned to a symbol frequency. Also, the advantages of using a digital phase-tooted loop (DPLL) to suppress side tones are described, and statistical properties of timing wave are derived. In addition, the overall performances of the symbol timing circuit are verified by computer simulation.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.601-604
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• 2002

In this paper, the timing do-skew modeling for a high speed logic tester channels is developed. The time delay of each channel in a logic tester are different from other channels and it can produce timing error in a test. To get the best timing accuracy in the test with a logic tester, the timing skew must be compensated. The timing skew of channels is due to the difference of time delay of pin-electronics devices composing channels and length of metal line placed on PCB. The expected timing difference of channels can be calculated according to the specifications of pin electronics devices and strip line modeling of PCB. With the calculated delay time, the timing skew compensation circuit has been designed. With the timing skew compensation circuit, the timing calibration of a logic tester can be peformed easily and automatically without other time measuring instruments. The calibration method can then be directly applied to logic testers in mass production lines.