• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.1016-1021
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• 2003

The overall size of electronic product is becoming small according to development of technology. Accordingly it is difficult to inspect these small components by human eyes. So, an automation system for inspecting them has been used. The existing system put microprocessor or Programmable Logic Controller (PLC) use. The structure of microprocessor-based controller and PLC use basically composed of memory devices such as ROM, RAM and I/O ports. Accordingly, the system is not only becomes complicated and enlarged but also higher price. In this paper, we implement FPGA-based One-chip Programmable Timing Controller for Inspecting Small components to resolve above problems and design the high performance controller by using VHDL. With fast development, the FPGA of high capacity that can have memory and PLL have been introduced. By using the high-capacity FPGA, the peripherals of the existent controller, such as memory, I/O ports can be implemented in one FPGA. By doing this, because the complicated system can be simplified, the noise and power dissipation problems can be minimized and it can have the advantage in price. Since the proposed controller is organized to have internal register, counter, and software routines for generating timing signals, users do not have to problem the details about timing signals and need to only send some values about an inspection system through an RS232C port. By selecting theses values appropriate for a given inspection system, desired timing signals can be generated.

• Nuclear Engineering and Technology
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• 제29권2호
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• pp.167-174
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• 1997

The method that the operating condition of Control Rod Drive Mechanism (CRDM) can be monitored without mounting sensors within CRDM housing was developed, and by using this developed method the closed-loop controller for the CRDM was designed which can optimize the performance and maximize the reliability of CRDM operation. Neural network is utilized as pattern recognition engine in detecting CRDM actuation. In this paper, most problems in previous open loop system are resolved. The control algorithms for closed-loop system ore developed and implemented within the hardware of timing controller based on microprocessor. All functions in the timing controller ore verified by means of real time CRDM simulator. The results show that the timing controller performs its intended functions properly.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 하계학술대회 논문집 B
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• pp.761-765
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• 1995

원자력발전소의 제어봉구동장치는 원자로의 압력경계 안에 설치되고 밀봉되므로 센서의 설치가 곤란하여 기존의 제어기는 개루프 형태의 제어기를 사용하고 있다. 본 논문에서는 기존 타이밍모듈의 문제점을 해결하기 위하여 제어봉구동장치 내부에 센서를 설치하지 않고도 제어봉구동장치의 작동 상황을 감시할 수 있는 방법을 개발하였다. 이 방법을 이용하여 제어봉 낙하방지, 정밀한 위치제어, 코일 수명연장의 특성이 있는 제어봉구동장치 타이밍 제어기를 폐루프 제어계통으로 설계하였다. 폐루프 제어개념에 의하여 개발된 알고리즘은 기존의 문제를 대부분 해결하였으며 계통의 성능 및 신뢰도가 향상되었다. 알고리즘 개발 및 시험 시, 여기서 설계한 실시간 제어봉구동장치 시뮬레이터를 사용하였고 현장에서 취득한 실제의 데이터와 함께 이 시뮬레이터를 이용하여 개발한 모든 알고리즘의 검증시험을 하였다. 검증결과 이 타이밍 제어기는 본래의 기능을 잘 수행하는 것으로 나타났다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.674-676
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• 2008

An electrostatic discharge (ESD) or a noise supplied from the outside has an effect on communication between the timing controller (TCON) and the memory element (EEPROM) through the interface between the timing controller and the memory element in liquid crystal displays (LCD). Therefore, we must apply ESD protection methods to LCD operating circuits for a normal operation. Our ESD protection circuit is to prevent from bi-directional communication errors between TCON and EEPROM due to an electrostatic discharge (ESD).

• International Journal of Automotive Technology
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• 제8권5호
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• pp.555-562
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• 2007

The Variable Valve Timing(VVT) system for high performance is a key technology used in newly developed engines. The system realizes higher torque, better fuel economy, and lower emissions by allowing an additional degree of freedom in valve timing during engine operation. In this study, a model-based control method is proposed to enable a fast and precise VVT control system that is robust with respect to manufacturing tolerances and aging. The VVT system is modeled by a third-order nonlinear state equation intended to account for nonlinearities of the system. Based on the model, a controller is designed for position control of the VVT system. The sliding mode theory is applied to controller design to overcome model uncertainties and unknown disturbances. The experimental results suggest that the proposed sliding mode controller is capable of improving tracking performance. In addition, the sliding mode controller is robust to battery voltage disturbance.

• 한국자동차공학회논문집
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• 제5권5호
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• pp.37-50
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• 1997

The objective of this paper is to study on the idle speed control using the fuzzy logic controller under load disturbance. The design procedure for fuzzy logic controller depends on the expert's knowledge or trial and error. The inputs of the fuzzy controller are error of rpm and variation of rpm. The output of the fuzzy controller is an ISC motor step and ignition timing. The airflow is controlled by the ISC motor movement and the idle speed is controlled by the airflow control and ignition timing control. During the control, air to fuel was checked by LAMBDA sensor. All experiments were performed in a real vehicle.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 학술대회지
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• pp.468-472
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• 2004

In this paper a VLSI design for the automatic magnetizing system has been presented. This is the design of a peripheral controller, which magnetizes CRTs and computers monitors and controls the automatic inspection system. We implemented a programmable peripheral interface(PPI) circuit of the control and protocol module for the magnetizer controller by using a O.8um CMOS SOG(Sea of Gate) technology of ETRI. Most of the PPI functions has been confirmed. In the conventional method, the propagation/ramp delay model was used to predict the delay of cells, but used to model on only a single cell. Later, a modified "apos;Linear delay predict model"apos; was suggested in the LODECAP(LOgic Design Capture) by adding some factors to the prior model. But this has not a full model on the delay chain. In this paper a new "apos;delay predict equationapos;" for the design of the timing control block in PPI system has been suggested. We have described the detail method on a design of delay chain block according to the extracted equation and applied this method to the timing control block design.

• 한국인터넷방송통신학회논문지
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• 제15권6호
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• pp.71-77
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• 2015

다중 모터를 효과적으로 제어하기 위하여 신호 측정 및 제어 알고리즘 수행 관련 스케쥴링 방법을 제안하고 제어 성능을 검토한다. 차량 내 전자제어시스템과 연계되어 동작하는 다중 모터 제어기는 CAN(Controller Area Network) 통신을 통하여 위치/속도 지령 값을 전달 받고 각 모터에 대한 위치/속도 제어, 전류 제어 등을 수행한다. 하나의 마이크로컨트롤러를 이용하여 다수 대 모터를 효과적으로 제어하기 위하여 내부 자원과 알고리즘 수행에 대한 적절한 스케쥴링이 중요하다. ADC(Analog to Digital Converter) 타이밍과 제어 알고리즘 수행 타이밍을 다양하게 변화시키며 실제 실험을 통하여 다중 모터 제어기의 성능을 분석한다.

• Journal of Positioning, Navigation, and Timing
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• 제2권1호
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• pp.67-74
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• 2013

In this study, a remote controller was designed using localization technique. The designed remote controller system consists of infrared transmit/receive module for time synchronization, ultrasonic transmit/receive module for measuring the TOA value, and micro-controller for processing the measured data value. For the position estimation method of remote controller, the Savarese method was used which does not have a problem of diverging solution depending on initial value. The noise included in the measured value was removed by separating the signal and noise with the use of EMD method which is the non-stationary signal analysis technique. The designed system was tested by constructing a simulation environment, and the improvement of accuracy and precision for the application of EMD method was examined.

• 전기전자학회논문지
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• 제17권2호
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• pp.168-175
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• 2013

고속의 동작 주파수를 갖는 메모리 제어기를 설계하여 PCB에서 고속 메모리와 통신을 할 경우 연결선의 길이와 배치에 따라 데이터가 전달되는 시간이 달라진다. 따라서 메모리 제어기를 설계한 뒤 PCB 상에서 메모리와 연결하여 동작시킬 때마다 이러한 지연시간이 달라져 제어기의 입출력 회로를 다시 설계하거나 초기화시 내부 설정을 바꾸어 주어야 한다. 본 논문에서는 이러한 문제를 해결하기 위해 제어기 내부에 초기화 단계에서 메모리에 테스트 패턴을 쓰고 읽으며 지연시간을 측정하고 적응적으로 지연시간을 고려한 입출력 회로를 구성하는 학습 방법을 제안한다. 제안한 학습 방법에서는 테스트 패턴을 쓰고 최소 시간 단위로 데이터를 읽는 타이밍을 바꾸어 가며 차례로 읽기를 시도하여 테스트 패턴이 정확히 읽히는 타이밍을 기억하여 초기화가 끝난 뒤 정상 동작을 시작하였을 때 학습 결과를 반영하여 메모리 접근을 시도한다. 제안한 학습 방법을 이용하면 PCB에 새로운 시스템을 구성하여도 초기화시 지연시간을 새로 설정하므로 제어기와 메모리의 통신 지연 문제를 해결할 수 있다. 제안한 방식은 고속의 SRAM, DRAM, 플래시 메모리 등에 사용 가능하다.