• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.5
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• pp.73-81
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• 1993

We have developed a system which can analyze the status of signal sent from/received to a signalling service equipment within the fully electronic switching system such as TDX-10. The system has such functions that acquire PCM signal of the preferred channel from the subhighway of the thirth-two channel by which a Universal Signal Tr ansceiver Unit(USTU) is connected with Time Switch Unit (TSU), and then classify the type of signal such as R2MFC/DTMF/CCT/VOICE, and determine the digit. Up to now, we have analyzed the frequency spec trum using the FFT. This paper describes the developement of PCM acquirer which can analyze the signal characteristics by acquiring the PCM signal in SHW(subhighway), and proposes the CZT(Chirp Z-Transform) algorithm. An algorithm which analyzes the acquired signal and determines the signal frequency and the corresponding power spectrum using the CZT is also discussed here.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.2
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• pp.75-80
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• 1994

AlAs/GaAs/AlAs RTDs(Resonant Tunneling Diodes) are fabricated and current-voltage properties of them are measured. At room temperature, peak to valley ratio is 2.4 NOT.AND.OR logic gates and Flip-Flop are fabricated using the bistable characteristics of RTDs. Although NOT.AND.OR logic gates need 5~8 transistors. only one RTD is sufficient to fabricate the logic gates. Since the switching time is very short(<10$^12$sec), it is possible to drive the semiconductor circuits fast and integrate them very large. And it is convinced the possibility of integrating RTDs to multilevel logic circuits by observing two peaks of similar current in the serial connection of two RTDs.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.2
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• pp.102-106
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• 2003

This paper describes novel low-power high-speed flip-flop called dual edge-triggered NAND keeper flip-flop (DETNKFF). The flip-flop achieves substantial power reduction by incorporating dual edge-triggered operation and by eliminating redundant transitions. It also minimizes the data-to-output latency by reducing the height of transistor stack on the critical path. Moreover, DETNKFF allows negative setup time to provide useful attribute of soft clock edge by incorporating the pulse-triggered operation. The proposed flip-flop was designed using a $0.35{\;}\mutextrm{m}$ CMOS technology. The simulation results indicate that, for the typical input switching activity of 0.3, DETNKFF reduces power consumption by as much as 21 %. Latency is also improved by about 6 % as compared to the conventional flip-flop. The improvement of power-delay product is also as much as 25 %.

• Biotechnology and Bioprocess Engineering:BBE
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• v.11 no.2
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• pp.110-115
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• 2006

We conducted a sensitivity analysis of the simulated moving bed (SMB) chromatography with the case model of the separation of two amino acids phenylalanine and tryptophan. We consider a four-zone SMB chromatography where the triangle theory is used to determine the operating conditions. Competitive Langmuir isotherm model was used to determine the adsorption isotherm. The finite difference method is used to solve nonlinear partial differential equation (PDE) systems numerically. We examined the effects of alterations in the operating conditions(feed-extract, feed-raffinate, eluent-extract, eluent-raffinate, recycle, and switching time) and the adsorption isotherm parameters (Langmuir isotherm parameters a and b) on SMB efficiency. The variation range of operating conditions and Langmuir isotherm a was between -50 and 50% of original value and the variation range of the Langmuir isotherm b was between $2.25^{-5}$ and $2.25^5$ times of original value.

• Proceedings of the KIEE Conference
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• 2006.04a
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• pp.87-89
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• 2006

A handover for DVB-H(Digital Video Broadcasting for Handheld) is the action of switching a receiver from receiving one signal to receiving another, when moving between the border of their coverage areas. This paper proposes new approaches for improving loss-free handover performance in the DVB-H networks. The proposed handover schemes are targeted to two different DVB-H receivers: One is for the receivers equipped with GPS devices. The other is for ones without GPS support. The first handover approach modifies the cell description table(CDT) proposed in the literature[1]. The second proposes a novel handover region estimation technique based on a new handover map table(HMT). This new handover approach estimates a predefined hand over region described in the HMT using measured RSSIs signal patterns. The estimation success rate is simulated and the benefits of the proposed method are discussed considering time and power consumption.

• Proceedings of the KIEE Conference
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• 1995.11a
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• pp.312-315
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• 1995

The base/gate drive suppression method proposed by Joshi and Bose is that which detects the output current polarity of the leg and, according to the polarity, suppresses the base/gate drive of one of the ore switching devices of the leg. This method has the merit that it does not have the conventional dead time problem, reduces the power loss of the driving circuit and others. But this method has difficulty in implementation. In this paper, a new base/gate drive suppression method by detecting not the output current polarity but the output voltage polarity is proposed. The proposed method is easier to implement than Joshi and Bose's method.

• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.471-475
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• 1997

PWM-VSI based ac-drives have high nonlinearity due to dead-time in the inverter and the voltage drop across the switching devices. In this paper, we introduced a new nonlinear model of PWM-VSl including parastic capacitor and also showed validity of the model by circuit simulations and experiments. Furthermore, we proposed an on-line identification algorithm for the uncertain model parameters.

• Proceedings of the KIEE Conference
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• 1995.11a
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• pp.242-245
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• 1995

In this paper the multiple three rectifiers for the power factor correction are proposed, analyzed and designed. The multiple three phase rectifiers draw sinusoidal ac currents from the ac voltage sources with nearly unity input power factor and operate with PWM making the control circuit simple and system cost low. Outstandingly it reduces the rated power capacity of devices and the input filter size by reducing input current ripples. Moreover design rules can be obtained from input and output current equations. With the proposed rules, input power factor and output power capacity are determined approximately. Finally these design rules are verified with computer simulations.

• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.25-27
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• 1997

The precise measurement of consumed power for a given time is very important in the energy management aspect. Up to days, most power meter has been used and designed for use on circuits in which the voltage and current are essentially sinusoidal. Recently the increase of switching element in power system causes the current and voltage with harmonics. Therefore, power energy involving harmonics is supplied to the system and the error of power measurement of watthour meter is existed. In this paper, we present a characteristic analysis by input frequency variation and analytical basis of induction watthour meter considering harmonics.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.60 no.1
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• pp.48-52
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• 2011

Over the years, traditionally, six-switch three-phase inverters have been widely utilized for variable speed alternating current motor drives. Recently, some efforts have been made on the application of four-switch three phase inverter for uninterruptible power supply and variable speed drives. This is due to some advantages of the four-switch three phase inverter over the conventional six-switch three-phase inverters such as reduced price due to reduction in number of switches, reduced switching losses, reduced number of interface circuits to supply logic signals for the switches, simpler control algorithms to generate logic signals, less chances of destroying the switches due to lesser interaction among switches, and less real-time computational burden. However such as slow di/dt and speed limitation, are the inherent characteristics and main drawbacks of the four-switch configuration. Those problems can be overcome in conjugation with Voltage-doublers which has additional advantage, such as unity power factor correction.