• The Transactions of the Korean Institute of Electrical Engineers
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• v.36 no.9
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• pp.623-635
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• 1987

A new suboptimal PWM is proposed, intended particularly for the reduction of acoustic noise and harmonics of the output current in the inverter-fed induction motor drive system. This strategy is based of the Regular PWM and applied optimal techniqe. And it could solve a problem that computation time is very much when switching strategy is determined at the Optimal PWM. In case that the number of switching increases infinitely, this strategy could determine the switching pattern, and can realize Online, Real time of microprocessor. Also, this strategy is applied to 1(Hp), three phase induction motor, and compared with the other PWMs. From the results, the validity of this strategy could be verified.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.152.1-152
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• 2001

This paper presents a high performance and cost effective way by using an FPGA circuit to implement torque controller so that the SRM can operate at high speed. In order to increase the operating speed, we need to implement both the torque and the current controllers by using an FPGA. However, it is difficult to implement all of the torque controller in the FPGA. Moreover, implementation of a time critical part is sufficient for improving the performance. One of the time critical part is the switching angle control. In this study, torque controller which calculate the switching on and commutation angles is implemented in PC because these angle are a function of rotor velocity which is varied slowly, and switching angle controller ...

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2004.10a
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• pp.345-348
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• 2004

Every bridge node participating in multiple piconets and forming a scatternet should schedule the inter-piconet traffics in an efficient manner. Frequent piconet switching due to short polling intervals for the links of a bridge node leads to considerable time slots loss caused by the guard time and power consumption for transceiving and processing. On the other hand, restrained piconet switching may result in failures of fulfilling QoS (Quality of Service) requirements for some links. Tn this paper, we present a QoS aware inter-piconet scheduling scheme minimizing the piconet switching events within guaranteed QoS requirements. According to simulation results, the proposed scheme is confirmed to have great improvement in throughput and number of switching events over the credit scheme as current inter-piconet scheduling scheme for the scatter mode.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.51 no.12
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• pp.664-669
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• 2002

In this paper the method to determine tire optimal switching instants in order to reduce the transient surges during switching not relevant to the neutral treatment of shunt reactors is presented. This method consists of the following two steps. First, the instants of the voltage peaks between the contacts of each poles and the voltage magnitude as well as the moments of the current zero crosses were found out analytically. Next, the instants of the contact touches or separations were determined in consideration of the rate of decrease of dielectric strength or a circuit breaker and the variation of the its operating time. The results obtained from the EMTP(Electromagnetic Transient Program) analysis studies show that the making instants are established at the peak voltage of each three poles for any conditions of a neutral point and the possible upper limited values of inrush currents due to the variation of the mechanical operating time can be estimated.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.4
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• pp.9-14
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• 1999

In this paper, we proposed a simultaneous switching noise (SSN) reduction technique in multi-layer boards (MLB) for high-speed digital applications and analyzed it using the Finite Difference Time Domain (FDTD) method. The new structure using conductive dielectric substrates is effective for the reduction of SSN couplings and resonances. The uniform insertion of the conducive layer reduced the SSN coupling and resonance by 85% and the partial insertion only around the edges reduced by 55% respectively.

• Proceedings of the KIEE Conference
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• 1994.11a
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• pp.178-180
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• 1994

In recent days, the inverter is widely used at the industrial applications. In the range lower than 100[kW], IGBT(Insulated Gate Bipolar Transistor) is most widely used as the switching device. In that case of IGBT, the rising time and the filling time are very short(about $200[ns]{\sim}300[ns]$). Especially for motor control applications, the switching frequency is required to be increased for better dynamic performance of the drive. However, the higher switching frequency leads to the unexpected problem occurs such as voltage spike due to stray inductance in the bus at switching instant. In this paper, a new methodology for reducing the stray inductance existing in the bus that induces the voltage spike will be presented.

• Journal of Broadcast Engineering
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• v.20 no.2
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• pp.215-223
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• 2015

Energy harvesting technique is an energy charging technique for communication device in energy-constrained environment. Recently, energy harvesting technique that harvests energy from wireless radio frequency signal is proposed. Representatively, there are time switching technique and power splitting technique. This paper proposes an optimal harvesting time allocation scheme in a wireless cognitive relay network when secondary user relay uses energy harvesting technique to transmit information. Secondary user relay receives information and energy simultaneously from the secondary user source's signal via time switching technique. We aim to maximize the instantaneous throughput by optimizing harvesting time of the secondary user relay. Simulation results show that using optimized harvesting time gets larger instantaneous throughput compared to using constant harvesting time.

• Journal of Power Electronics
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• v.16 no.2
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• pp.425-435
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• 2016

This paper presents a comprehensive theoretical analysis and an accurate calculation method of the dead-time required to achieve zero-voltage-switching (ZVS) in a battery charger with the phase-shifted full-bridge (PSFB) topology. Compared to previous studies, this is the first time that the effects of nonlinear output filter inductance, varied Miller Plateau length, and blocking capacitors have been considered. It has been found that the output filter inductance and the Miller Plateau have a significant influence on the dead-time for ZVS when the load current varies a lot in battery charger applications. In addition, the blocking capacitor, which is widely used to prevent saturation, reduces the circulating current and consequently affects the setting of the dead-time. In consideration of these effects, accurate analytical equations of the dead-time range for ZVS are deduced. Experimental results from a 1.5kW PSFB battery charger prototype shows that, with the proposed analysis, an optimal dead-time can be selected to meet the specific requirements of a system while achieving ZVS over wide load range.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.11
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• pp.5223-5242
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• 2017

In the last decade, the 2.4 GHz band of IEEE 802.11 WLANs has become heavily congested due to the explosive increase in demand of Wi-Fi connectivity. With the current deployment of enterprise WLANs, channel switching mechanism continues to exhibit inefficiencies because it cannot adapt to real-time channel condition and the inability to support seamless channel switching. Software Defined Networking (SDN) as an emerging architecture is promising to introduce flexibility and programmability for wireless network management. Leveraging SDN to existing enterprise WLANs, channel switching method can be improved significantly. This paper presents a software-defined enterprise WLAN framework with a load aware automatic channel switching solution, which utilizes AP load and channel interference factor (CIF) to provide seamless channel switching. Two automatic channel switching algorithms named Single Switch (SS) and Double Switch (DS) are proposed to improve the overall user experience and the experience of users with highest traffic load respectively. Experiment results demonstrate that our solution can efficiently improve user experience in terms of jitter, transmission delay and network throughout when compared to the conventional channel switching mechanism.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.131-131
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• 2009

Silicon Carbide (SiC) is a material with a wide bandgap (3.26eV), a high critical electric field (~2.3MV/cm), a and a high bulk electron mobility ($\sim900cm^2/Vs$). These electronic properties allow high breakdown voltage, high-speed switching capability, and high temperature operation compared to Si devices. Although various SiC DMOSFET structures have been reported so far for optimizing performances, the effect of channel dimension on the switching performance of SiC DMOSFETs has not been extensively examined. This paper studies different channel dimensons ($L_{CH}$ : $0.5{\mu}m$, $1\;{\mu}m$, $1.5\;{\mu}m$) and their effect on the the device transient characteristics. The key design parameters for SiC DMOSFETs have been optimized and a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. has been used to understand the relationship. with the switching characteristics. To investigate transient characteristic of the device, mixed-mode simulation has been performed, where the solution of the basic transport equations for the 2-D device structures is directly embedded into the solution procedure for the circuit equations. We observe an increase in the turn-on and turn-off time with increasing the channel length. The switching time in 4H-SiC DMOSFETs have been found to be seriously affected by the various intrinsic parasitic components, such as gate-source capacitance and channel resistance. The intrinsic parasitic components relate to the delay time required for the carrier transit from source to drain. Therefore, improvement of switching speed in 4H-SiC DMOSFETs is essential to reduce the gate-source capacitance and channel resistance.