• Proceedings of the IEEK Conference
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• 2009.05a
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• pp.305-307
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• 2009

When we design the control system used Programmable Logic Controller(PLC), we program the main algorithm by Ladder Diagram(LD) among the standard language. We can substitute the select sequence function by the unique sequence. We can implement this function by the delay time. Therefore this thesis show the select sequence function by the unique sequence and we confirmed its feasibility through actual example.

• Korean Journal of Computational Design and Engineering
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• v.6 no.4
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• pp.244-253
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• 2001

For more complete process planning, machining sequence determination is critical to attain machining economics. Although many studies have been conducted in recent years, most of them suggests the non-unique machining sequences. When the tool approach directions(TAD) are considered fur a feature, both machining time and number of setups can be reduced. Then, the unique machining sequence can be extracted from alternate(non-unique) sequences by minimizing the idle time between operations within a sequence. This study develops an algorithm to generate the best machining sequence for composite prismatic features in a vertical milling operation. The algorithm contains five steps to produce an unique sequence: a precedence relation matrix(PRM) development, tool approach direction determination, machining time calculation, alternate machining sequence generation, and finally, best machining sequence generation with idle times. As a result, the study shows that the algorithm is effective for a given composite feature and can be applicable fur other prismatic parts.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.5
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• pp.952-958
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• 1994

In this paper a method calculates the time offset between a binary sequence and its shifted sequence based on the number theoretic approach is presented. Using this method the time offset between a binary sequence and its shifted sequence can be calculated. It has been recongnized that the defining the reference (zero-offset) sequence is important in synchronous code division multiple access(CDMA) system since the same spreading sequence are used by the all base station. The time offset of the sequence with respect to the zero offset sequence are used to distinguish signal received at a mobile station from different base stations. This paper also discusses a method that defines the reference sequence.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.5
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• pp.422-428
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• 1988

An iterative learning control system is a control system which makes system outputs follow desired outputs by iterating its trials over a finite time interval. In a discrete time system, we proposed one method in which present control inputs can be obtained by a linear combination of the input sequence and time-shifted error sequence at previous trial. In contrast with a continous time learning control system which needs differential opreration of an error signal, the time shift operation of the error sequence is simpler in a computer control system and its effectiveness is shown by a simulation.

• Journal of KIISE:Databases
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• v.30 no.4
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• pp.372-380
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• 2003

Temporal databases support time-varying events so that conventional aggregate functions are extended to be processed with time for temporal aggregate functions. In the previous approach, it is done repeatedly to find time intervals and is calculated the result of each interval whenever target events are different. This paper proposes a method which processes temporal aggregate function queries using time point sequence. We can make time point sequence storing the start time and the end time of events in temporal databases in advance. It is also needed to update time point sequence due to insertion or deletion of events in temporal databases. Because time point sequence maintains the information of time intervals, it is more efficient than the previous approach when temporal aggregate function queries are continuously requested, which have different target events.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.12
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.43 no.3
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• pp.10-20
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• 2020

This paper presents a method to measure the similarity of assigned jobs in the gravure printing operation based on the chromaticity and color sequence, and order the jobs accordingly. The proposed dispatching rule can be used to fulfill diverse manufacturing site requirements because the parameters can be adjusted to prioritize chromaticity and color sequence. In general, dispatching rules either ignore the job-changing time or require that the time be clearly defined. However, in the gravure printing operation targeted in this study, it is difficult to apply the general dispatching rule because of the difficulties in quantifying the job-changing time. Therefore, we propose a method for generalizing assignment rules of the job planner, allocating relative similarity among assigned jobs, and determining the sequence of jobs accordingly. Chromaticity priority is determined by the arrangement of the color assignments in the printing operation; color sequence priority is determined by the addition, deletion, or change in a specific color sequence. Finally, the job similarity is determined by the dot product of the chromaticity and color sequence priorities. Implementation of the proposed dispatching rule at an actual manufacturing site showed the planner present the same job order as that obtained using the proposed rule. Therefore, this rule is expected to be useful in industrial sites where clear quantification of the job-changing time is not possible.

• Journal of Welding and Joining
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• v.27 no.2
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• pp.57-62
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• 2009

This research was carried out to improve the productivity in the subassembly process of shipbuilding through optimal work planning for the shortest work time. The work time consist of welding time, moving time of gantry, teaching time of robot and robot motion time. The shortest work time is accomplished by even distribution of work and the shortest welding sequence. Even distribution of work was done by appling the simple algorithm. The shortest work sequence was determined by using GA. The optimal work planning decreased the total work time of the subassembly process by 4.1%. The result showed the effectiveness of the suggested simple algorithm for even distribution of work and GA for the shortest welding sequence.

• Journal of the Korean Magnetic Resonance Society
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• v.1 no.1
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• pp.7-20
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• 1997

The mapping of the spin-spin relaxation time T2 in pixed-by-pixel was suggested as a quantitative diagnostic tool in medicine. Although the CPMG pulse sequence has been known to be the best pulse sequence for T2 measurement in physics NMR, the supplied pulse sequence by the manufacture of MRI system was able to obtain the maximum of 4 CPMG images. Eight or more images with different echo time TEs are required to construct a reliable T2 map, so that two or more acquisitions were required, which easily took more than 10 minutes. 4-echo CPMG imaging pulse sequence was modified to generate the maximum of 8 MR images with evenly spaced echo time TEs. In human MR imaging, since patients tend to move at least several pixels between the different acquisitions, 8-echo CPMG imaging sequence reduces the acquisition time and may remove any misregistration of each pixel's signal for the fitting T2. The resultant T2 maps using the theoretically simulated images and using the MR images of the human brain suggested that 8 echo CPMG sequence with short echo spacing such as 17∼20 msec can give the reliable T2 map.

• Journal of the Korea Society of Computer and Information
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• v.21 no.3
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• pp.57-64
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• 2016

This paper deals with the PCB assembly time minimization problem that the PAP (pick-and-placement) machine pickup the K-weighted group of N-components, loading, and place into the PCB placement location. This problem considers the rotational turret velocity according to component weight group and moving velocity of distance in two component placement locations in PCB. This paper suggest heavy-weight component group first pick-and-place strategy that the feeder sequence fit to the placement location Hamiltonean cycle sequence. This algorithm applies the quadratic assignment problem (QAP) that considers feeder sequence and location sequence, and the linear assignment problem (LAP) that considers only feeder sequence. The proposed algorithm shorten the assembly time than iATMA for QAP, and same result as iATMA that shorten the assembly time than ATMA.