• 한국초전도학회:학술대회논문집
• /
• v.11
• /
• pp.43-43
• /
• 2001

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
• /
• v.8 no.6
• /
• pp.939-946
• /
• 2018

In this work, we present simple schematics for a three-terminal graphene-based nanoelectromechanical switch with the vertical electrode, and we investigated their operational dynamics via classical molecular dynamics simulations. The main structure is both the vertical pin electrode grown in the center of the square hole and the graphene covering on the hole. The potential difference between the bottom gate of the hole and the graphene of the top cover is applied to deflect the graphene. By performing classical molecular dynamic simulations, we investigate the nanoelectromechanical properties of a three-terminal graphene-based nanoelectromechanical switch with vertical pin electrode, which can be switched by the externally applied force. The elastostatic energy of the deflected graphene is also very important factor to analyze the three-terminal graphene-based nanoelectromechanical switch. This simulation work explicitly demonstrated that such devices are applicable to nanoscale sensors and quantum computing, as well as ultra-fast-response switching devices.

• Progress in Superconductivity
• /
• v.3 no.1
• /
• pp.70-73
• /
• 2001

We report the spin injection and transport properties of three terminal devices of Co/Au/$YBa_2$$Cu_3$$O_{y}$(F/N/S) tunnel junctions by injection of spin-polarized quaiparticles using a cobalt ferromagnetic injector. The observed current gain depends on the thickness of Au interlayer and is directly related to the nonequilibrium magnetization due to spin relaxation effects. The tunnel characteristic of a F/N/S tunnel junctions exhibited a zero bias conductance peak (ZBCP). The suppression of the ZBCP was observed due to the suppression of Andreev reflection at the interface, which is due to the spin scattering processes at the interface between a ferromagnetic and a d-wave superconductor.r.

• Journal of Institute of Control, Robotics and Systems
• /
• v.17 no.3
• /
• pp.223-228
• /
• 2011

In this paper, we proposed a technique to recognize three states in stance phase of gait cycle. Walking assistive devices are used to help the elderly people walk or to monitor walking behavior of the disabled persons. For the effective assistance, they adopt an intelligent sensor system to understand user's current state in walking. There are three states in stance phase; Loading Response, Midstance, and Terminal Stance. We developed a foot pressure sensor using 24 FSRs (Force Sensing/Sensitive Resistors). The foot pressure patterns were integrated through the interpolation of FSR cell array. The pressure patterns were processed to get the trajectories of COM (Center of Mass). Using the trajectories of COM of foot pressure, we can recognize the three states of stance phase. The experimental results show the effective recognition of stance phase and the possibility of usage on the walking assistive device for better control and/or foot pressure monitoring.

• Proceedings of the Korean Magnestics Society Conference
• /
• 2003.06a
• /
• pp.262-262
• /
• 2003

Creating a new spin-based electronics (often called "spin-electronics" or "spintronics") is one of the hot topics in the current solid-state physics and electronics research. In order to utilize the spin degree of freedom in solids, particularly in semiconductors the current electronics is based on, we need to fabricate appropriate materials, understand and control the spin-dependent phenomena. In this ta1k, I will review the recent deve1opments of epitaxial ferromagnetic hetero structures based on semiconductors towards spintronics. This includes the semiconductor materials and hetero structures having high ferromagnetic transition temperature (III-V based alloy magnetic semiconductors, Mn-delta-doped magnetic semiconductors, and related heterostructures), spin-dependent transport and tunneling, and their device applications (tunneling magnetoresistance devices and three-terminal devices). Future issues and prospects will be also discussed.

• Proceedings of the Optical Society of Korea Conference
• /
• 2005.07a
• /
• pp.204-205
• /
• 2005

Studies on display has been requested some major changes due to the high growth of the handheld terminal market. Therefore, the self emitting OLED(Organic Light Emitting Diode) has been interested as a next generation flat plane display because of its preeminent characteristics such as quick response characteristics, higher performance viewing angle, low power consumption, and panel floating. However, a trend of the display market is moving to three dimensional image processing instead of two dimensional flat display and various researches on display using hologram makes up for the difficulty in three dimensional display using typical flat display. In this study the Lenticular Screen Printing method is presented so that it can be applicable to organic semiconductor display devices and makes possible three dimensional display using flat display for complement the drawback of inorganic semiconductor.

• Physical Therapy Korea
• /
• v.28 no.2
• /
• pp.117-122
• /
• 2021

Background: Flat-back posture refers to a posture in which the pelvis is tilted backward, the lumbar spine is bent, the upper thoracic spine is increasingly bent, and the lower thoracic spine is straight. Given that most of the day is spent sitting, we need to develop exercise programs and devices that are suitable for people who spend less time exercising than sitting. Objects: This study investigated the effects of resistance footrest exercise on spine posture angles in visual display terminal (VDT) workers with flat back. Methods: We measured the upper lumbar angle (ULA) and lower lumbar angle (LLA) using a flexible ruler for the ULA and LLA. Then, after 1 week of resistance footrest exercise designed to strengthen the lumbar spine musculature, we measured these angles again. We measured each angle three times and then compared measurements from before and after exercise. Results: There were no significant differences in the ULA following the strengthening exercise, but significant differences were observed in LLA. Conclusion: The resistance footrest exercise strengthened the muscles affecting the pelvic and lumbar lordotic angles, and increases in the LLA were changed. This suggests that the role of the lower lumbar spine in the lumbar lordotic curve is greater than that of the upper lumbar spine. In addition, considering the contemporary tendency to lead fairly sedentary lives, these results indicate that exercising while seated can be effective.

• The Transactions of the Korean Institute of Electrical Engineers
• /
• v.39 no.3
• /
• pp.263-272
• /
• 1990

In the variable speed driving system of a three phase induction motor controlled by a PWM inverter, the output terminal contains considerable amount of harmonic components of the voltage waveform due to the switching action of semiconductor devices, causing torque ripples, acoustic noise and oscillation of the motor. This paper describes a new algorithm which eliminates the harmonics and controls the fundamental voltage in three phase PWM inverter output waveform. The new algorithm utilizes the technique of particular harmonics elimination (PHE) by walsh series in three phase PWM inverter output waveform. A microprocessor (8086 CPU)-controlled three phase induction motor system is described to realize this algorithm. The system is designed for 3 phase output voltage in the 1-60Hz interval where 5th and 7th harmonics, and 5th, 7th, 11th, and 13th harmonics are eliminated. Also, the fundamental wave amplitude is designed to be proportional to the output frequency. The performance of the proposed method shows sufficient elimination of the harmonics and also reduction of computation time which determines switching pattern. The proposed PWM pattern by Walsh series, is effective not only to induction motors but also to other electromagetic equipments such as voltage regulators and UPS.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.4 no.3
• /
• pp.196-203
• /
• 2004

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

• The Transactions of the Korean Institute of Electrical Engineers D
• /
• v.54 no.8
• /
• pp.475-481
• /
• 2005

In the existing ICT technique, the mounted electronic devices on the printed circuit board are tested whether the devices are good or not by comparing and measuring the value of the devices after separating the devices to be tested from around it based on the guarding method. But, in case that resistance, inductor and capacitor are configured as a parallel circuit on the circuit pattern, values for each device can not be measured because the total impedance value of the parallel circuit is measured. Accordingly, it is impossible to test whether the parallel circuit is good or not in case that the measured impedance value is within the tolerance error. Also, it is difficult to identify that which device among R, L and C of the parallel circuit is bad in case that the measured impedance value is out of the tolerance error. Accordingly, this paper proposes a test method which can enhance the quality and productivity by separating and measuring accurately R, L and C components from the RLC parallel circuits on the device-mounted printed circuit board. First, the RLC parallel circuit to be test is separated electrically from around it using three-terminal guarding technique. And then R, L and C values are computed based on the total impedance values and phase angles between voltage and current of the parallel circuit measured from two AC input signals with other frequency, Finally, the availability and accuracy of the proposed test method is verified by reviewing the simulation results.