• Journal of Power Electronics
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• v.10 no.3
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• pp.262-269
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• 2010

This paper proposes a practical design for a Cascaded H-Bridge Multilevel (CHBM) inverter based on Power Electronics Building Blocks (PEBB) and high performance control to improve current control and increase fault tolerance. It is shown that the expansion and modularization characteristics of the CHBM inverter are improved since the individual inverter modules operate more independently, when using the PEBB concept. It is also shown that the performance of current control can be improved with voltage delay compensation and the fault tolerance can be increased by using unbalance three-phase control. The proposed design and control methods are described in detail and the validity of the proposed system is verified experimentally in various industrial fields.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.2 no.2
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• pp.64-70
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• 1988

In many applications of inverter system, it is desirable to obtain an AC output voltage with variable frequency and amplitude. For the variable-speed AC motor drive, the system is one major area of application for the variable-frequency inverter. V ariable~voltage variable-frequency sinusoidal output in three-phase inverter is possible by employing the techniques developed. In this paper, the technique of particular harmonics elimination(PHE) in three-phase PWM inverter-output waveforms is introduced. The required switching patterns are determind on personal computer. Results are stored in look-up table in EPROM and used to control the switching of the inverter devices. The experimental results indicate that the loss in an induction motor is minimized to a degree by using this algorithm. The proposed PWM pattern is effective not only to the induction motor but also to the other electromagnetic machine such as Voltage Regulator, UPS.

• Proceedings of the KIEE Conference
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• 2007.11b
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• pp.311-313
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• 2007

Three phase power flow is commonly considered exclusively for the distribution systems, where single or double phase circuits may be present and loads may not always balanced between the three phases. This paper deals with modelling and analysis of grid connected photovoltaic (PV) system in three-phase power flow, with the consideration of the PV inverter output power limitations.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.55 no.6
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• pp.299-305
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• 2006

In this paper, we suggest a new space vector PWM modulation method with very short processing time which does not need identification of nearest three vectors(NTV) and duty ratio for each vector. The suggested PWM method makes mean value of phase voltage to be same as reference during every modulation period by use of a triangle in small hexagon on multi-level vector space. This paper described the suggested modulation method can be successfully applied to the space vector modulation use of multi-level inverter by computer simulations and experiments.

• Proceedings of the KIEE Conference
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• 1997.07f
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• pp.2259-2261
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• 1997

In this paper, control scheme of the three phase VSI(Voltage Source Inverter) for 200KVA UPS is described. The proposed controller is designed to robust against parameter variations, disturbances and load change using PI controller. The switching pattern is determined to Ramp Comparison Method. The inverter provides pure sinusoidal output voltage with very low THD (Total Harmonic Distortion). Finally, the performance of the proposed inverter is shown by experimental result.

• Proceedings of the KIEE Conference
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• 1997.07f
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• pp.2104-2106
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• 1997

In order to develop the three phase GTO CSI with double recovery path of commutation energy by passive devices (LCD), we studied the clamping circuit to protect switching device and energy recovery circuit to recover absorbed energy of capacitor and DC inductor. In this paper, we investigated how DC input power is increased or decreased according to energy recovery path with or not in the three phase GTO current source inverter, we used a induction motor as inverter load, and controlled a induction motor with v/f constant control. Experimental results show that dissipated DC power is decreased in $9{\sim}14%$ by double recovery path. We also confirmed that the characteristics is met as compare simulation results with experimental results according to each frequency.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.232-235
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• 2001

This paper presents a circuit of the quasi-resonant DC link to achieve soft-switching three phase inverter using intelligent IGBT power module. The soft-switching operation in this circuit is confirmed simulation and experimental results. Its conductive noise is measured for electrical AC motor drive as compared with that of the conventional hard switching inverter.

• Proceedings of the KIEE Conference
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• 2003.04a
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• pp.154-156
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• 2003

3상 4레그(leg) VSI(Voltage Source Inverter)는 독립된 3개의 출력전압을 합성할 수 있다. 따라서 전압 합성에 있어서 3개의 자유도를 갖는다. 본 논문에서는 3상 4레그 VSI를 위한 PWM방법에 대해서 설명한다. 3상 4레그 VSI를 위한 기존의 PWM기술은 3-D SVPWM으로 그 구현 방법에 있어서 많은 양의 계산과 테이블을 필요로 하였다. 하지만, 본 논문에서 제안 한 방법은 3상 3레그 VSI경우에 적용되었던 옵셋(offset) 전압의 개념을 사용한다. 또한 단일 반송파를 이용하여 폴(Pole)전압과 비교함으로써 PWM을 구현하기 때문에 그 적응이 매우 간단하다. 본 논문에서는 기존의 3-D SVPWM과 제안한 방법이 해석적으로 동일한 방법임을 증명하였으며, 3상 4레그 VSI에서 합성가능한 3자유도의 전압범위를 계산하였다. 마지막으로 이를 실험을 통하여 검증하였다.

• Proceedings of the KIEE Conference
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• 1994.07a
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• pp.495-497
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• 1994

Given the constraint of the AC input power factor and the DC-link voltage and current ripple in voltage source inverter, minimizing the size and cost of the DC-link fitter components is very important. This paper presents a procedure for the selection of DC-link filler element values in a three-phase PWM voltage source inverter-fed induction motor drive system, which can not only satisfy the requirements for the system performance but also minimize the filter size.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.225-227
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• 2008

This paper deals with the implementation on a Field Programmable Gate Array (FPGA) of PWM switching patterns for a voltage multilevel inverter. The reference data in main microcontroller is transmitted to the FPGA through 16 general purpose I/O ports. Herein, three-phase reference voltage signals are addressed by the last 2-bit (bit 15-14) and their data are assigned in remaining 14-bit, respectively. The carrier signals are created by 16-bit counter in up-down counting mode inside FPGA according to desirable topology. Each reference signal is compared with all carrier signals to generate corresponding PWM switching patterns for control of the multilevel inverter. Useful advantages of this scheme are easy implementation, simple software control and flexibility in adaptation to produce many PWM signals. Some simulations and experiments are carried out to validate the proposed method.