• 한국정보통신학회논문지
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• 제24권2호
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• pp.325-328
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• 2020

This paper demonstrated a voltage-controlled oscillator (VCO) using cost-effective (1-poly 6-metal) mixed signal standard CMOS process. To have the high-quality factor inductor in LC resonator with thin metal thickness, patterned-ground shields (PGS) was adopted under the spiral to effectively reduce the ac current of low resistive Si substrate. And, because of thin top-metal compared with that of RF option (2 ㎛), we make electrically connect between the top metal (M6) and the next metal (M5) by great number of via array along the metal traces. The circuit operated from 2.48 GHz to 2.62 GHz tuned by accumulation-mode varactor device. And the measured phase noise of LC VCO has -123.7 dBc/Hz at 1MHz offset at 2.62 GHz and the dc-power consumption shows 2.07 mW with 1.8V supply voltage, respectively.

• Transactions on Electrical and Electronic Materials
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• 제3권3호
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• pp.14-17
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• 2002

The HDP (High Density Plasma) CVD process consists of a simultaneous sputter etch and chemical vapor deposition. As CMOS process continues to scale down to sub- quarter micron technology, HDP process has been widely used fur the gap-fill of small geometry metal spacing in inter-metal dielectric process. However, HBP CVD system has some potential problems including plasma-induced damage. Plasma-induced gate oxide damage has been an increasingly important issue for integrated circuit process technology. In this paper, thin gate oxide charge damage caused by HDP deposition of inter-metal dielectric was studied. Multiple step HDP deposition process was demonstrated in this work to prevent plasma-induced damage by introducing an in-situ top SiH$_4$ unbiased liner deposition before conventional deposition.

• 한국전기전자재료학회논문지
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• 제13권9호
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• pp.729-734
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• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• 한국전기전자재료학회논문지
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• 제16권2호
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• pp.138-143
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• 2003

A double spiral thin-film inductor with a NiFe magnetic core is integrated with DC-DC converter IC. The NiFe core is deposited on a polyimide film as the thinckness of NiFe is 2.5~3.5 ${\mu}$m. Then, copper conductor line is deposited on the NiFe core with double spiral structure. Process integration is performed by sequential processes of etching the polyimide film deposited both top and bottom of the NiFe core and electroplation copper conductor line from exposed metal pad of the DC-DC converter IC. Process integration is simplified by elimination planarization process for top core because the proposed thin-film inductor has a bottom NiFe core only. Inductor of the fabricated monolithic DC-DC converter IC is 0.53 ${\mu}$H when the area of converter IC and thin-film inductor are 5X5$\textrm{mm}^2$ and 3.5X2.5$\textrm{mm}^2$, respectively. The efficiency is 72% when input voltage and output voltage are 3.5 V and 6 V, respectively at the operation frequency of 8 MHz.

• 전자공학회논문지D
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• 제35D권9호
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• pp.77-86
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• 1998

본 논문에서는 정전용량형 센서 칩과 CMOS 인터페이스 칩으로 구성된 투 칩 집적화 습도 센서를 개발하였다. (100) 실리콘 기판위에 폴리이미드 박막을 이용해서 제작된 습도 센서 칩은 넓은 습도 및 온도 범위에 걸쳐 우수한 직선성(0.72%FS), 낮은 히스테리시스(<3%), 작은 온도계수(-0.0285∼-0.0542 pF/K)를 나타내었다. 40℃/90%RH에서 9주동안 방치한 후 측정된 정전용량은 약 2∼3% 변하였다. 신호처리 회로는 1.2-㎛, one poly double metal CMOS 공정으로 제작하였다. 측정된 센서 출력 전압은 상대습도에 비례해서 변하였으며, 이론치와 잘 일치하였다.

• Transactions on Electrical and Electronic Materials
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• 제18권6호
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• pp.341-344
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• 2017

Infrared (IR) filters were developed to implement integrated three-dimensional (3D) image sensors that are capable of obtaining both color image and depth information at the same time. The combination of light filters applicable to the 3D image sensor is composed of a modified IR cut filter mounted on the objective lens module and on-chip filters such as IR pass filters and color filters. The IR cut filters were fabricated by inorganic $SiO_2/TiO_2$ multilayered thin-film deposition using RF magnetron sputtering. On-chip IR pass filters were synthetized by dissolving various pigments and dyes in organic solvents and by subsequent patterning with photolithography. The fabrication process of the filters is fairly compatible with the complementary metal oxide semiconductor (CMOS) process. Thus, the IR cut filter and IR pass filter combined with conventional color filters are considered successfully applicable to 3D image sensors.

• 대한전자공학회논문지SD
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• 제44권10호
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• pp.33-37
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• 2007

본 논문에서는 vertical shunt symmetric inductor를 이용하여 CMOS LNA의 설계에 있어서 회로의 면적을 줄이는 설계기술 및 구현에 관한 내용을 제시하고자 한다. 본 연구에 있어서 vertical shunt symmetric inductor는 LNA의 입력단과 출력단을 3GHz로 정합하기 위해서 사용되었다. 이렇게 구현된 보다 면적에 있어서 효율적인 증폭기를 0.18um digital logic공정으로 구현되었다. 본 논문에서는 일반적으로 LNA에서 사용하고 있는 inductor를 이용하는 경우와, vertical shunt symmetric inductor를 이용하여 LNA를 설계하는 경우에 대한 부분을 비교하였고, 최종적으로 면적에 효율적인 회로설계 기술을 제시하고자 한다.

• Korean Chemical Engineering Research
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• 제47권2호
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• pp.141-149
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• 2009

초고속 연산용 CMOS(complementary Metal Oxide Semiconductor) 배선재료로 사용되고 있는 구리(Cu)가, 기가급 메모리 소자용 금속 배선 물질에도 사용이 시작되면서 구리 박막에 대한 재료 및 공정이 새로운 조명을 받고 있다. 반도체 금속 배선에 사용하는 수 nm 두께의 구리 박막의 형성에 전해도금(electrodeposition)과 무전해 도금(electroless deposition) 같은 전기화학적 방법을 이용하게 되어서 표면 처리, 전해액 조성과 같은 중요한 요소에 대한 최신 연구 동향을 요약하였다. 구리 박막에서 구리 배선을 제작하여야 하므로 새로운 패턴 기술인 상감기법이 도입되어, 구리도금과 상감기법과의 공정 일치성 관점에서 전해도금과 무전해 도금의 요소 기술에 대해 기술하였다. 구리보다 비저항이 낮아 차세대 소자용 배선에 있어서 적용이 예상되는 은(Ag)을 전기화학적 방법으로 금속 배선에 적용하는 최신 연구에 대하여도 소개하였다.

• 한국전자통신학회논문지
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• 제14권1호
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• pp.87-96
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• 2019

유기 박막 트랜지스터 (OTFT) 백플레인을 이용한 유연한 유기 발광 다이오드 (OLED) 디스플레이가 연구되고 있다. OLED 디스플레이의 구동을 위해서 게이트 드라이버가 필요하다. 저온, 저비용 및 대 면적 인쇄 프로세스를 사용하는 디스플레이 패널의 내장형 게이트 드라이버는 제조비용을 줄이고 모듈 구조를 단순화한다. 이 논문에서는 유연한 OLED 디스플레이 패널의 내장형 게이트 드라이버 제작을 위하여 OTFT를 사용한 의사 CMOS (pseudo complementary metal oxide semiconductor) 로직 게이트를 구현한다. 잉크젯 인쇄형 OTFT 및 디스플레이와 동일한 프로세스를 사용하여 유연한 플라스틱 기판 상에 의사 CMOS 로직 게이트가 설계 및 제작되며, 논리 게이트의 동작은 측정 실험에 의해 확인된다. 최대 1 kHz의 입력 신호 주파수에서 의사 CMOS 인버터의 동작 결과를 통하여 내장형 게이트 드라이버의 구현 가능성을 확인하였다.

• 한국초전도ㆍ저온공학회논문지
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• 제20권4호
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• pp.20-25
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• 2018

Niobium nitride (NbN) superconducting thin films with the thickness of 100 and 400 nm have been deposited on the surfaces of silicon oxide/silicon substrates using a sputtering method. Their superconducting properties have been evaluated in terms of the transition temperature, critical magnetic field, and critical current density. In addition, the NbN films were patterned in a line with a width of $10{\mu}m$ by a reactive ion etching (RIE) process for their characterization. This study proves the applicability of the standard complementary metal-oxide-semiconductor (CMOS) process in the fabrication of superconducting thin films without considerable degradation of superconducting properties.