• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.2
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• pp.325-328
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• 2020

This paper demonstrated a voltage-controlled oscillator (VCO) using cost-effective (1-poly 6-metal) mixed signal standard CMOS process. To have the high-quality factor inductor in LC resonator with thin metal thickness, patterned-ground shields (PGS) was adopted under the spiral to effectively reduce the ac current of low resistive Si substrate. And, because of thin top-metal compared with that of RF option (2 ㎛), we make electrically connect between the top metal (M6) and the next metal (M5) by great number of via array along the metal traces. The circuit operated from 2.48 GHz to 2.62 GHz tuned by accumulation-mode varactor device. And the measured phase noise of LC VCO has -123.7 dBc/Hz at 1MHz offset at 2.62 GHz and the dc-power consumption shows 2.07 mW with 1.8V supply voltage, respectively.

• Transactions on Electrical and Electronic Materials
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• v.3 no.3
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• pp.14-17
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• 2002

The HDP (High Density Plasma) CVD process consists of a simultaneous sputter etch and chemical vapor deposition. As CMOS process continues to scale down to sub- quarter micron technology, HDP process has been widely used fur the gap-fill of small geometry metal spacing in inter-metal dielectric process. However, HBP CVD system has some potential problems including plasma-induced damage. Plasma-induced gate oxide damage has been an increasingly important issue for integrated circuit process technology. In this paper, thin gate oxide charge damage caused by HDP deposition of inter-metal dielectric was studied. Multiple step HDP deposition process was demonstrated in this work to prevent plasma-induced damage by introducing an in-situ top SiH$_4$ unbiased liner deposition before conventional deposition.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.9
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• pp.729-734
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• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.2
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• pp.138-143
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• 2003

A double spiral thin-film inductor with a NiFe magnetic core is integrated with DC-DC converter IC. The NiFe core is deposited on a polyimide film as the thinckness of NiFe is 2.5~3.5 ${\mu}$m. Then, copper conductor line is deposited on the NiFe core with double spiral structure. Process integration is performed by sequential processes of etching the polyimide film deposited both top and bottom of the NiFe core and electroplation copper conductor line from exposed metal pad of the DC-DC converter IC. Process integration is simplified by elimination planarization process for top core because the proposed thin-film inductor has a bottom NiFe core only. Inductor of the fabricated monolithic DC-DC converter IC is 0.53 ${\mu}$H when the area of converter IC and thin-film inductor are 5X5$\textrm{mm}^2$ and 3.5X2.5$\textrm{mm}^2$, respectively. The efficiency is 72% when input voltage and output voltage are 3.5 V and 6 V, respectively at the operation frequency of 8 MHz.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.9
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• pp.77-86
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• 1998

A two-chip humidity sensor system has been developed which consists of a capacitive sense element die and a CMOS interface chip. The sense element was fabricated using thin polyimide films on (100) silicon substrate and showed excellent linearity(0.72%FS), low hysteresis (<3%) and low temperature coefficient(-0.0285 ~-0.0542pF/K) over a wide range of relative humidity and temperature. The capacitance-relative humidity characteristic exhibited a drift of 2~3% after 9 weeks of exposure to 4$0^{\circ}C$/90%RH. The signal-conditioning circuitry was fabricated using an 1.2- ${\mu}{\textrm}{m}$, one poly double metal CMOS process. The measured output voltage of the sensor system was directly proportional to relative humidity and showed good agreement with theory.

• Transactions on Electrical and Electronic Materials
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• v.18 no.6
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• pp.341-344
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• 2017

Infrared (IR) filters were developed to implement integrated three-dimensional (3D) image sensors that are capable of obtaining both color image and depth information at the same time. The combination of light filters applicable to the 3D image sensor is composed of a modified IR cut filter mounted on the objective lens module and on-chip filters such as IR pass filters and color filters. The IR cut filters were fabricated by inorganic $SiO_2/TiO_2$ multilayered thin-film deposition using RF magnetron sputtering. On-chip IR pass filters were synthetized by dissolving various pigments and dyes in organic solvents and by subsequent patterning with photolithography. The fabrication process of the filters is fairly compatible with the complementary metal oxide semiconductor (CMOS) process. Thus, the IR cut filter and IR pass filter combined with conventional color filters are considered successfully applicable to 3D image sensors.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.10
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• pp.33-37
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• 2007

This paper presents the implementation technique to reduce circuit area occupation in designing Low Noise Amplifier (LNA) using vertical shunt symmetric inductor. We applied a vertical shunt symmetric inductor to match the input and output in 3 GHz CMOS LNA to reduce the circuit area. This size efficient amplifier has been designed in a $0.18\;{\mu}m$ digital logic CMOS process. In this paper, the case of conventional asymmetric inductor, and vertical shunt symmetrical inductor with a relatively higher number of turns have been compared in order to efficient a size efficient CMOS LNA design method while still retaining the circuit operation characteristics.

• Korean Chemical Engineering Research
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• v.47 no.2
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• pp.141-149
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• 2009

The Cu thin film material and process, which have been already used for metallization of CMOS(Complementary Metal Oxide Semiconductor), has been highlighted as the Cu metallization is introduced to the metallization process for giga - level memory devices. The recent progresses in the development of key elements in electrochemical processes like surface pretreatment or electrolyte composition are summarized in the paper, because the semiconductor metallization by electrochemical processes such as electrodeposition and electroless deposition controls the thickness of Cu film in a few nm scales. The technologies in electrodeposition and electroless deposition are described in the viewpoint of process compatibility between copper electrodeposition and damascene process, because a Cu metal line is fabricated from the Cu thin film. Silver metallization, which may be expected to be the next generation metallization material due to its lowest resistivity, is also introduced with its electrochemical fabrication methods.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.1
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• pp.87-96
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• 2019

Flexible organic light-emitting diode (OLED) displays with organic thin-film transistors (OTFTs) backplanes have been studied. A gate driver is required to drive the OLED display. The gate driver is integrated into the panel to reduce the manufacturing cost of the display panel and to simplify the module structure using fabrication methods based on low-temperature, low-cost, and large-area printing processes. In this paper, pseudo complementary metal oxide semiconductor (CMOS) logic gates are implemented using OTFTs for the gate driver integrated in the flexible OLED display. The pseudo CMOS inverter and NAND gates are designed and fabricated on a flexible plastic substrate using inkjet-printed OTFTs and the same process as the display. Moreover, the operation of the logic gates is confirmed by measurement. The measurement results show that the pseudo CMOS inverter can operate at input signal frequencies up to 1 kHz, indicating the possibility of the gate driver being integrated in the flexible OLED display.

• Progress in Superconductivity and Cryogenics
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• v.20 no.4
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• pp.20-25
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• 2018

Niobium nitride (NbN) superconducting thin films with the thickness of 100 and 400 nm have been deposited on the surfaces of silicon oxide/silicon substrates using a sputtering method. Their superconducting properties have been evaluated in terms of the transition temperature, critical magnetic field, and critical current density. In addition, the NbN films were patterned in a line with a width of $10{\mu}m$ by a reactive ion etching (RIE) process for their characterization. This study proves the applicability of the standard complementary metal-oxide-semiconductor (CMOS) process in the fabrication of superconducting thin films without considerable degradation of superconducting properties.