• Journal of the Microelectronics and Packaging Society
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• v.21 no.2
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• pp.85-89
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• 2014

We propose the new fabrication method of a 70 nm half-pitch wire grid polarizer with high performance using magnetic soft mold. The device is a form of aluminium gratings on a PET(Polyethylene phthalate) substrate whose size of $3cm{\times}3cm$ is compatible with a TFT_LCD(Tin Flat Transistor Liquid Crystal Display) panel. A magnetic soft mold with a pitch of 70 nm is fabricated using two-step replication method. As a result, we get a NWGP pattern which has 70.39 nm line width, 64.76 nm depth, 140.78 nm pitch, on substrate. The maximum and minimum transmittances of the NWGP at 800 nm are 75% and 10%, respectively. This work demonstrates a unique cost-effective solution for nanopatterning requirements in consumer electronics components.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.239-242
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• 1998

Ca $F_2$ films have superior gate insulator properties than conventional gate insulator such as $SiO_2$, Si $N_{x}$, $SiO_{x}$, and T $a_2$ $O_{5}$ to the side of lattice mismatch between Si substrate and interface trap charge density( $D_{it}$). Therefore, this material is enable to apply Thin Film Transistor(TFT) gate insulator. Most of gate oxide film have exhibited problems on high trap charge density, interface state in corporation with O-H bond created by mobile hydrogen and oxygen atom. This paper performed Ca $F_2$ property evaluation as MIM, MIS device fabrication. Ca $F_2$ films were deposited at the various substrate temperature using a thermal evaporation. Ca $F_2$ films was grown as polycrystalline film and showed grain size variation as a function of substrate temperature and RTA post-annealing treatment. C-V, I-V results exhibit almost low $D_{it}$(1.8$\times$10$^{11}$ $cm^{-1}$ /le $V^{-1}$ ) and higher $E_{br}$ (>0.87MV/cm) than reported that formerly. Structural analysis indicate that low $D_{it}$ and high $E_{br}$ were caused by low lattice mismatch(6%) and crystal growth direction. Ca $F_2$ as a gate insulator of TFT are presented in this paper paperaper

• Korean Journal of Materials Research
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• v.11 no.6
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• pp.527-532
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• 2001

Dry etching of copper film using $O_2$ plasma and H(hfac) has been investigated. A one-step process consisting of copper film oxidation with an $O_2$ plasma and the removal of surface copper oxide by the reaction with H(hfac) to form volatile Cu(hfac)$_2$ and $H_2O$ was carried but. The etching rate of Cu in the range from 50 to 700 /min was obtained depending on the substrate temperature, the H(hfac)/O$_2$ flow rate ratio, and the plasma power. The copper film etch rate increased with increasing RF power at the temperatures higher than 215$^{\circ}C$. The optimum H(hfac)/O$_2$ flow rate ratio was 1:1, suggesting that the oxidation process and the reaction with H(hfac) should be in balance. Cu patterning using a Ti mask was performed at a flow rate ratio of 1:1 on 25$0^{\circ}C$\ulcorner and an isotropic etching profile with a taper slope of 30$^{\circ}$was obtained. Cu dry patterning with a tapered angle which is necessary for the advanced high resolution large area thin film transistor liquid-crystal displays was thus successfully obtained from one step process by manipulating the substrate temperature, RF power, and flow rate ratio.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.144-144
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• 2012

최근 폴리머를 기판으로 하는 고속 Flexible TFT (Thin film transistor)나 고효율의 박막 태양전지(Thin film solar cell)를 실현시키기 위해 낮은 비저항(resistivity)을 가지며, 높은 홀 속도(carrier hall mobility)와 긴 이동거리를 가지는 다결정 반도체 박막(poly-crystalline semiconductor thin film)을 만들고자 하고 있다. 지금까지 다결정 박막 반도체를 만들기 위해서는 비교적 높은 온도에서 장시간의 열처리가 필요했으며, 이는 폴리머 기판의 문제점을 야기시킬 뿐 아니라 공정시간이 길다는 단점이 있었다. 이에 반도체 박막의 재결정화 온도를 낮추어 주는 metal (Al, Ni, Co, Cu, Ag, Pd, etc.)을 이용하여 결정화시키는 방법(MIC)이 많이 연구되어지고 있지만, 이 또한 재결정화가 이루어진 반도체 박막 안에 잔류 금속(residual metal)이 존재하게 되어 비저항을 높이고, 홀 속도와 이동거리를 감소시키는 단점이 있다. 이에 본 실험은, 종래의 MIC 결정화 방법에서 이용되어진 금속 증착막을 이용하는 대신, HIPIMS (High power impulse magnetron sputtering)와 PIII&D (Plasma immersion ion implantation and deposition) 공정을 복합시킨 방법으로 적은 양의 알루미늄을 이온주입함으로써 재결정화 온도를 낮추었을 뿐 아니라, 잔류하는 금속의 양도 매우 적은 다결정 반도체 박막을 만들 수 있었다. 분석 장비로는 박막의 결정화도를 측정하기 위해 GIXRD (Glazing incident x-ray diffraction analysis)와 Raman 분광분석법을 사용하였고, 잔류하는 금속의 양과 화학적 결합 상태를 알아보기 위해 XPS (X-ray photoelectron spectroscopy)를 통한 분석을 하였다. 또한, 표면 상태와 막의 성장 상태를 확인하기 위하여 HRTEM(High resolution transmission electron microscopy)를 통하여 관찰하였다.

• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.50-52
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• 2006

본 논문은 고성능 다결정 실리콘(Poly-Si) 박막 트랜지스터 (Thin Film Transistor)에서 단일 수직 그레인 경계(Single Perpendlcular Grain Boundary)가 고온 캐리어 스트레스(Hot Carrier Stress) 및 정전류 안정성 평가에서 어떠한 효과를 보이는가에 대해서 살펴보았다. 고온 캐리어 스트레스 하에서($V_G=V_{TH}+1V,\;V_D$ =12V),그레이 경계가 없는 다결정 실리콘 TFT와 비교했을 때 그레인 경계를 가지고 있는 다결정 실리를 TFT는 전기 전도(Electric Conduction)에 작용하는 자유 캐리어(Free Carrier)의 개수가 적기 때문에 상대적으로 더욱 우수한 전기적 특성을 나타낸다. 먼저 1000초 동안 고온 캐리어 스트레스를 가해준 결과 단일 그레인 경계를 가진 다결정 실리콘에서의 트랜스 컨덕턴스(Transconductance)의 이동 정도는 5% 미만으로 확인되었다. 반면에 같은 스트레스 조건 하에서 그레인 경계가 존재하지 않는 다결정 실리콘의 경우에는 그 이동 정도가 약 25%에 달하는 것으로 측정되었다. 다음으로 정전류 스트레스(Constant Current Stress) 인가시, 수직형 그레인 경계가 채널 영역 내에 존재하지 않는 다결정 실리콘 TFT는 드레인 접합 부분의 전계 세기를 비교했을 때, 그레인 경계를 가지고 있는 다결정 실리콘 TFT보다 상대적으로 낮은 원 인 때문에 적게 열화되는(Degraded) 특성을 확인할 수 있었다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.96-96
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• 2007

Low voltage organic TFTs (OTFTs) and ZnO based TFTs (<5V), utilizing room temperature deposited $Bi_{1.5}Zn_{1.0}Nb_{1.5}O_7$ (BZN) thin films were recently reported, pointing to high-k gate insulators as a promising route for realizing low voltage operating flexible electronics. $Bi_{1.5}Zn_{1.0}Nb_{1.5}O_7$ (BZN) thin film is one of the most promising materials for gate insulator because of its large dielectric constant (~60) at room temperature. However their tendency to suffer from relatively high leakage current at low electric field (>0.3MV/cm) hinder the application of BZN thin films for gate insulator. In order to improve leakage current characteristics of BZN thin film, we mixed 30mol% MgO with 70mol% BZN and their dielectric and electric properties were characterized. We fabricated field-effect transistors with transparent oxide semiconductor ZnO serving as the electron channel and high-k $(Bi_{1.5}Zn_{1.0}Nb_{1.5}O_7)_{0.7}(MgO)_{0.3}$ as the gate insulator. The devices exhibited low operation voltages (<4V) due to high capacitance of the $(Bi_{1.5}Zn_{1.0}Nb_{1.5}O_7)_{0.7}(MgO)_{0.3}$ dielectric.

• Bulletin of the Korean Chemical Society
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• v.33 no.2
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• pp.420-425
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• 2012

The new organic semiconductors which are composed of divinylbenzene core unit and alkoxynaphthalene on both sides, 1,4-bis-2-(6-octyloxy)naphthalen-2-ylvinylbenzene (BONVB), 1,4-bis-2-(6-decyloxy)naphthalen-2-ylvinylbenzene (BDNVB) and 1,4-bis-2-(6-dodecyloxy)naphthalen-2-ylvinylbenzene (BDDNVB) were synthesized by Wittig reaction. The structures of obtained BONVB, BDNVB and BDDNVB were confirmed by FT-IR and mass spectroscopy. UV-absorption of thin film showed H-aggregates and J-aggregates due to closely packed structure between adjacent molecules. The characterization of vacuum-evaporated films by Xray diffraction (XRD) and atomic force microscopy (AFM) showed that the chain length of alkoxy group affects the crystallinity and morphology. BONVB with octyloxy group showed the mobility of $0.011cm^2/V{\cdot}s$, on/off ratio of $1.31{\times}10^5$, and a subthreshold slope of 0.93 V.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.287-298
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• 2007

A two-dimensional treatment of the potential distribution under the depletion approximation is presented for poly-crystalline silicon thin film transistors. Green's function approach is adopted to solve the two-dimensional Poisson's equation. The solution for the potential distribution is derived using Neumann's boundary condition at the silicon-silicon di-oxide interface. The developed model gives insight into device behavior due to the effects of traps and grain-boundaries. Also short-channel effects and drain induced barrier lowering effects are incorporated in the model. The potential distribution and electric field variation with various device parameters is shown. An analysis of threshold voltage is also presented. The results obtained show good agreement with simulated results and numerical modeling based on the finite difference method, thus demonstrating the validity of our model.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.95-96
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• 2008

A new voltage-driven pixel circuit using soluble-processed organic thin film transistors (OTFTs) for an active matrix organic light emitting diode (AMOLED) is proposed. The proposed circuit is composed of four switching TFTs, one driving TFT and one storage capacitor. The proposed circuit can compensate for the degradation of OLED current caused by the threshold voltage shift of the OTFT. The simulation results show that the variation of OLED current corresponding to a 3V threshold voltage shift is decreased by 30% compared to the conventional 2TlC structure.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.3
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• pp.130-136
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• 1989

Electrical transport and thermally induced metastability in hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs) using boron-doped amorphous silicon as an active layer have been studied. The device characteristics n-channel and p-channel operations. The thermal quenching experiments on amorphous silicon-silicon nitride ambipolar TFT give clear evidence for the co-existence of two distinct metastable changes. The densities of metastable active dopants and dangling bonds increase with the quenching temperature. On the other hand, the interface state density appears to decrease with increasing quenching temperature.