• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.12
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• pp.2202-2211
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• 2006

EXT3NS is a special-purpose file system for large scale multimedia streaming servers. It is built on top of streaming acceleration hardware device called Network-Storage card. The EXT3NS file system significantly improves streaming performance by eliminating memory-to-memory copy operations, i.e. sending video/audio from disk directly to network interface with no main memory buffering. In this paper, we design and implement a buffer cache mechanism, called PMEMCACHE, for EXT3NS file system. We also propose a buffer cache replacement method called ONS for the buffer cache mechanism. The ONS algorithm outperforms other existing buffer replacement algorithms in distributed multimedia streaming environment. In EXT3NS with PMEMCACHE, operation is 33MB/sec and random read operation is 2.4MB/sec. Also, the buffer replacement ONS algorithm shows better performance by 600KB/sec than other buffer cache replacement policies. As a result PMEMCACHE and an ONS can greatly improve the performance of multimedia steaming server which should supportmultiple client requests at the same time.

• Proceedings of the Korea Information Processing Society Conference
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• 2023.11a
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• pp.1127-1128
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• 2023

캐시는 현대 컴퓨터 시스템에서 중요한 성능 개선 요소 중 하나로, 효율적인 데이터 저장 및 액세스를 보장한다. 교체 정책은 캐시의 한정된 용량 내에서 어떤 데이터를 보관하고 어떤 데이터를 대체할지 결정하는 데 중요한 역할을 한다. 이 논문은 Pseudo LRU 와 LRU 교체 정책을 대상으로 cache 에서의 throughput 과 gate count 를 각각 비교한다. LRU 방식을 적용한 cache 와 Pseudo LRU 방식을 적용한 cache 는 Locality 0 과 100 에서 0.001GB/s 미만의 차이를 보이며 각각 0.095GB/s, 0.211GB/s 로 동일했으며 Gate Count 는 각각 134,516 과 130,016 으로 4500 의 감소 효과가 있었다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.1
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• pp.224-240
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• 1996

It is common sense for at least one or more levels of cache memory to be used in these day's computer systems. In this paper, the impact of the internal cache memory organization on the performance of the computer is investigated by using a simulator program, which is wirtten by authors and run on SUN SPARC workstation, with several real execution, with several real execution trace files. 280 cache organizations have been simulated using n-way set associative mapping and LRU(Least Recently Used) replacement algorithm with write allocation policy. As a result, 16-way setassociative cache is the best configuration, and when we select 256KB cache memory and 64 byte line size, the bus traffic ratio was decreased compared to that of the noncache system so that a single bus could support almost 7 processors without any delay and degradationof high ratio(hit ratio was 99.21%). The smaller the line size we choose, the little lower hit ratio we can get, but the more processors can be supported by a single bus(maximum 18 processors). Therefore, using a proper cache memory organization can make a single bus structure be able to support multiple processors without any performance degradation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.68-75
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• 2009

As the recent performance of microprocessor is improving quickly, the necessity of cache is growing because of the increase of the access time of main memory. Every block of direct-mapped cache maps to one cache line. Although the mapping rule is simple, if different blocks map to one cache line, the miss ratio will be higher than the set-associative cache due to conflicts. In this paper, for the improvement of the direct-mapped cache of OpenRISC, 4-way set-associative cache is proposed. Four blocks of the main memory of the proposed cache map to one cache line so that the miss ratio is less than the direct-mapped cache. Pseudo-LRU Policy, which is one of the Line Replacement Policies, is used for decreasing the number of bits that store LRU value. The OpenRISC core including the 4-way set-associative cache was verified with FPGA emulation. As the result of performance measurement using test program, the performance of the OpenRISC core including the 4-way set-associative cache is higher than the previous one by 50% and the decrease of miss ratio is more than 15%.

• The KIPS Transactions:PartA
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• v.9A no.2
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• pp.163-170
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• 2002

Previous buffer cache schemes for continuous media file system only exploited the sequentiality of continuous media accesses and didn't consider looping references. However, in some video applications like foreign language learning, users mark the scene as loop area and then application automatically playbacks the scene several times. In this paper, we propose a novel buffer cache scheme for continuous media file system that sequential and looping references exist together. Proposed scheme increases the cache hit ratio by detecting reference pattern of files and appling an appropriate replacement policy to each file.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.7
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• pp.369-376
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• 2002

Although LRU is not adequate for database that has non-uniform reference pattern, it has been adopted in most database systems due to the absence of the proper alternative. We analyze database block reference pattern with the realistic database trace. Based on this analysis, we propose a new cache replacement policy. Trace analysis shows that extremely non-popular blocks take up about 70 % of the entire blocks. The influence of recency on blocks' re-reference likelihood is at first strong due to temporal locality, however, it rapidly decreases and eventually becomes negligible as stack distance increases. Based on this observation, RCB(Reference Characteristic Based) cache replacement policy, which we propose in this paper, classifies the entire blocks into four block groups by blocks' recency and re-reference likelihood, and operates different priority evaluation methods for each block group. RCB policy evicts non-popular blocks more quickly than the others and evaluates the priority of the block by frequency that has not been referenced for a long time. In a trace-driven simulation, RCB delivers a better performance than the existing polices(LRU, 2Q, LRU-K, LRFU). Especially compared to LRU. It reduces miss count by 5~l2.7%. Time complexity of RCB is O(1), which is the same with LRU and 2Q and superior to LRU-K(O(log$_2$N)) and LRFU(O(l) ~ O(log$_2$N)).

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.4
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• pp.1-8
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• 2011

Traditional transactional memory systems are no longer able to guarantee the performance of diverse applications with overflowed transactions since there is the drawback that tracking the data for logging is difficult. Especially, this mechanism has a disadvantage of increasing communication delay for sustaining the state which is required to detect the conflict on the overflowed transactions from the first level cache in the transactional memory systems. To address this point, we have focused on the cache architecture of the systems to reduce the overhead caused by overflows and cache misses. In this paper, we present Supportive Cache which reduces additional overhead during transactions. Supportive Cache performs a parallel look-up with L1 private cache and uses the same replacement policy as L1 private cache. We evaluate the performance of the proposed design by comparing LogTM-SE with and without Supportive Cache. The simulation results show that our system improves the performance by 37% on average, compared to the original LogTM-SE which uses the same hardware resource.

• Proceedings of the IEEK Conference
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• 2000.11c
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• pp.51-54
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• 2000

Due to the emerging of high-speed network, lots of interests of access to remote data have increased. Those interests motivate using of Cooperative Caching that uses remote cache like local cache by sharing other clients' cache. The conventional algorithm like GMS(Global Memory Service) has some disadvantages that occurred bottleneck and decreasing performance because of exchanges of many messages to server or manager. On the other hand, Hint-based algorithm resolves a GMS's server bottleneck as each client has hint information of all blocks. But Hint-based algorithm also causes some problems such as inaccurate information in it, if it has too old hint information. In this paper, we offer the policy that supplement bottleneck and inaccuracy； by using file identifier that can search for the lookup table and by exchanging oldest block information between each client periodically.

• Proceedings of the Korean Information Science Society Conference
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• 2001.04a
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• pp.10-12
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• 2001

웹에서 도큐먼트 재배치 정책은 캐쉬(cache)성능을 향상시키기 위한 방법중의 하나이다. 이 방법을 웹 캐쉬 공간이 한정되어 있으며 새로운 도큐먼트를 위한 공간을 만들기 위해 어느 도큐먼트를 축출(remove)[2]할 것인가를 결정하고 새로운 도큐먼트를 갱신(update)[6]하기 위한 방법을 제공한다. 도큐먼트 재배치 정책으로는 LRU(Least Recently Used), LFU(Least Frequently Used)등과 같은 방법이 보편적을 사용되고 있으나, 웹에 적용하기에는 몇 가지 단점이 있다. 본 논문에서는 LRU, LFU등의 도큐먼트 재배치 정책을 이용하면서도 웹에 적용하기 위해 몇 가지 단점을 보완한 LRFU(Least Recently/Frequently Used)[4]기법을 사용한다. 또한 본 논문에서는 인터넷(internet) 사용자의 지수적인(exponential) 증가와 이로 인한 병목현상(bottleneck)의 발생을 전제로 하여, 캐쉬성능을 향상시키기 위한 다각적인 시도로 지역성(locality), 일관성(consistency)[7][5], 확장성(scalability)[5]등의 문제에 관한 논의와 기존의 방법과는 다른 도큐먼트 재배치 정책에의 접근을 시도한다.

• Journal of the Korea Society of Computer and Information
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• v.27 no.7
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• pp.9-16
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• 2022

Today, with the advent of the 4th industrial revolution, IoT (Internet of Things) systems are advancing rapidly. For this reason, a various application with high-performance and large-capacity are emerging. Therefore, there is a need for low-power and high-performance memory for computing systems with these applications. In this paper, we propose an effective structure for the L1 cache memory, which consumes the most energy in the computing system. The proposed cache system is largely composed of two parts, the L1 main cache and the buffer cache. The main cache is 2 banks, and each bank consists of a 2-way set association. When the L1 cache hits, the data is copied into buffer cache according to the proposed algorithm. According to simulation, the proposed L1 cache system improved the performance of energy delay products by about 65% compared to the existing 4-way set associative cache memory.