• 한국통신학회논문지
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• 제25권4A호
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• pp.558-565
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• 2000

조합형 회로에 대한 테스트 패턴 생성의 문제는 거의 만족할 만한 수준에 도달한데 반해 순차형 회로에 대한 테스트 패턴 생성은 여전히 많은 연구를 필요로 하고 있다. 본 연구에서는 효율적인 검사 패턴 생성을 위하여 검사 패턴 생성 과정에서 탐색되어지는 상태 공간 정보의 효율적으로 저장하고, 그렇게 저장된 상태 공간 정보를 이용하여 효율적으로 검사패턴을 생성하는 알고리즘을 제안한다. 그리고 제안된 알고리즘과 기존의 결정적 검사 패턴 생성 알고리즘을 실험을 통하여 비교함으로써 제안된 알고리즘의 효율성을 검증한다.

• 전자공학회논문지C
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• 제35C권4호
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• pp.30-37
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• 1998

In this paper, we propose a test generation method for large scale sequential circuits based on circuit partitioning to increase the size of circuits that the implicit product machine traversal (IPMT) method can handle. Our method paratitions a circuit under test into subset circuits with only single output, and performs a partial scan design using the state transtition cost that represents a degree of the connectivity of the subset circuit. The IPMT method is applied to the partitioned partial scan circuits in test generation. Experimental results for ISCAS89 benchmark circuits with more thatn 50 flip-flops show that our method has generated test patterns with almost 100% fault coverage at high speed by use of 34%-73% scanned flip-flops.

• 대한전자공학회논문지SD
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• 제40권2호
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• pp.126-136
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• 2003

본 논문에서는 최근 많은 연구대상이 되고 있는 oscillation test methodology (OTM)의 파라메트릭 고장에 대한 커버리지를 높일 수 있는 방법을 제안한다. OTM은 테스트 입력신호가 별도로 필요없는 장점으로 인해 효율적인 built-in self test (BIST) 기술로서도 많은 관심의 대상이 되어 왔다. 그러나 아직 여러 가지 면에서 좀더 연구개발이 필요한 상태이며, 따라서 본 논문에서는 그 성능을 향상시킬 수 있는 방안을 제안한다.

• 한국정보과학회논문지:소프트웨어및응용
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• 제37권10호
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• pp.768-772
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• 2010

콘콜릭 테스트는 높은 테스트 커버리지를 달성하기 위해 실제 프로그램 수행과 심볼릭 수행을 결합하여 테스트 데이터를 생성한다. CREST는 콘콜릭 테스팅을 구현한 대표적인 open-source인 테스트 도구이다. 그러나 현재 CREST는 기본적으로 프로그램의 모든 가능한 실행 경로들을 탐색하는 것을 목적으로 한다. 이 때문에 특정 분기 또는 블록만을 테스트하는 경우에는 비효율적일 수 있다. 이 논문에서는 프로그램 상의 한 분기 또는 블록을 주고 이률 실행할 수 있는 테스트 데이터를 생성하는 목적 지향 콘콜릭 테스트 방법을 제안한다.

• 전자공학회논문지B
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• 제30B권4호
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• pp.85-91
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• 1993

In this paper, we propose the test pattern generation algorithm of the embedded faulty MUX for the prevention of misdiagnosis of digital systems. When the system is partitioned with a large number of functional blocks, if the faults are exsisted in a embedded MUX then it can not diagnose the wanted observation of functional block. The proposed test pattern generstion algorithm can apply the MUXs that designd 2-level and multi-level both. Fault coverage becomes 100% and so it is no necessary of the additional fault simulation and the proposed algorithm that have the regulary and easily generated 2d test patterns. And we confirmed that the reduction of test cost becomes 85%, compared with the conventional segmentation testing scheme.

• 정보처리학회논문지D
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• 제13D권4호
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• pp.573-582
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• 2006

소프트웨어를 블랙박스 테스트 하려면 대상 소프트웨어에 적절한 데이터를 주어 실행해 보아야 한다. 효과적인 테스트가 되기 위해서 테스트 케이스의 선택뿐만 아니라 테스트 케이스가 어떻게 표현되었는가가 중요하다. 또한 정적인 테스트 작업에도 테스트를 위한 체크리스트가 어떻게 작성되었는지에 따라 테스트 작업의 효율성이 좌우된다. 이 논문에서는 비효율적이며 문제가 있는 테스트 케이스와 체크 리스트들을 리엔지니어링 하는 방법을 제시하고 이를 실험 하였다. 임베디드 시스템의 일종인 디지털 방송수신 장치에 탑재된 소프트웨어를 대상으로 하여 이미 사용 중인 테스트 케이스의 효율성과 적합성을 따져보고 이를 리엔지니어링 하였다. 리엔지니어링 한 후의 테스트 케이스의 산출물이 테스트 시간과 커버리지 측면에서 얼마나 효과적인지를 살펴보았다. 또한 제품 계열 개념의 소프트웨어를 테스트하기에 적합하도록 테스트 케이스를 재사용 또는 재구조화 하는 방법도 연구하였다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2004년도 ICCAS
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• pp.981-985
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• 2004

In this paper we designed the motor control IP Core and evaluate its quality from the viewpoint of IP reuse. The most attractive merit of this methodology, so called IP-based hardware design, is hardware reuse. Although various vendors designed hardware with the same specification and got the same functional results, all that IPs is not the same quality in the reuse aspect. As tremendous calls for SoC have been increased, associated research about IP quality standard, VSIA(Virtual Socket Interface Alliance) and STARC(Semiconductor Technology Academic Research Center), has been doing best to make the IP quality evaluation system. And they made what conforms to objective IP design standard. We suggest the methodology to evaluate our own designed motor control IP quality with this standard. To attain our goal, we designed motor control IP that could control the motor velocity and position with feedback compensation algorithm. This controller has some IP blocks : digital filter, quadrature decoder, position counter, motion compensator, and PWM generator. Each block's functionality was verified by simulator ModelSim and then its quality was evaluated. To evaluate the core, We use Vnavigator for lint test and ModelSim for coverage check. During lint process, We adapted the OpenMORE's rule based on RMM (Reuse Methodology Manual) and it could tell us our IP's quality in a manner of the scored value form. If it is high, its quality is also high, and vice versa. During coverage check ModelSim-SE is used for verifying how our test circuits cover designs. This objective methods using well-defined commercial coverage metrics could perform a quantitative analysis of simulation completeness. In this manner, We evaluated the designed motor control IP's quality from the viewpoint of reuse. This methodology will save the time and cost in designing SoC that should integrate various IPs. In addition to this, It can be the guide for comparing the equally specified IP's quality. After all, we are continuously looking forward to enhancing our motor control IP in the aspect of not only functional perfection but also IP reuse to prepare for the SoC-Compliant motor control IP design.

• Journal of Computing Science and Engineering
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• 제9권3호
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• pp.142-154
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• 2015

Fault localization techniques help locate faults in source codes by exploiting collected test information and have shown promising results. To precisely locate faults, the techniques require a large number of test cases that sufficiently exercise the executable statements together with the label information of each test case as a failure or a success. However, during the process of software development, developers may not have high-coverage test cases to effectively locate faults. With the test case generation techniques, a large number of test cases without expected outputs can be automatically generated. Whereas the execution results for generated test cases need to be inspected by developers, which brings much manual effort and potentially hampers fault-localization effectiveness. To address this problem, this paper presents a method to select a few test cases from a number of test cases without expected outputs for result inspection, and in the meantime selected test cases can still support effective fault localization. The experimental results show that our approach can significantly reduce the number of test cases that need to be inspected by developers and the effectiveness of fault localization techniques is close to that of whole test cases.

• 한국정보처리학회논문지
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• 제6권11호
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• pp.3070-3076
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• 1999

Petri net is one of the effective modeling techniques which analyzes and designs concurrent and asynchronous systems. CPN is an extended Petri net which has color tokens. In this paper, we propose a new test case generation method using CPN. It transforms Estelle Specification into CPN, which is applicable to Design/CPN. It also generates UIO and subtour from OG and descriptor, which are resulted from Design/CPN. Using the proposed method, we can get more improved test coverage than existing methods. Therefore, more effective protocol conformance testing could be conducted. The test case generating method will be the basis of the automatic testing environmented.

• 천문학회보
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• 제40권1호
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• pp.57.3-57.3
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• 2015

We present a test observation result of the KMTNet Intensive Nearby Southern Galaxy group Survey (KINGS). The KINGS is designed to study nearby galaxy groups (NGC 55, NGC 253, NGC 5128, and M83 groups), taking the advantage of the wide field coverage of the KMTNet. The main goal of the KINGS is to produce extensive catalogs of dwarf galaxies, ultra compact dwarfs (UCDs), and intraglobular clusters in the galaxy groups. We will also investigate the spatial distribution of intragroup light in each group. We present a progress report of the project based on the test BVI observations of two galaxy groups. We discuss the result from the test observation and possible improvement for future observations.