• 전기의세계
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• v.22 no.1
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• pp.42-51
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• 1973

The contriving equivalent circuit of single phase induction motor which does not separate the primary leakage reactance and the secondary leakage reactance by the revolving field theory, and the graphically calculating method of the characteristics with T-type circle diagram of three phase induction motor which does not suppose the primary leakage reactance can be drawn up only by the no load test, the lock test, and measuring the resistance of stator winding are suggested in this paper. The method which can calculate the parameters of the equivalent circuit and the characteristics with no load test, lock test and measuring resistance of stator windings is suggested in this paper. Considered the exciting current in lock test, we could calculate very accurate characteristics of the single phase induction motor.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1089-1095
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• 2005

This paper presents a new low-cost Built-In Self-Test (BIST) circuit for 50Hz low noise amplifier (LNA). The BIST circuit is designed for system-on-chip (SoC) transceiver environment. The proposed BIST circuit measures the LNA specifications such as input impedance, voltage gaih, noise figure, and input return loss all in a single SoC environment.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.25 no.6
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• pp.75-81
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• 2011

This study aims to research and analyze the cause and countermeasures of the short-circuit test failures of the distribution transformer, which captures failure share at the highest level when carrying out its performance test. For this purpose, the research was done on the basis of 77 failure cases out of 998 tests in total performed by the Korea Electrotechnology Research Institute(KERI) from 2004 to 2010. Based on the research, the paper also includes analysis of the causes of the short-circuit test failures in its early stage of transformer development and proposes its countermeasures accordingly.

• The Transactions of the Korean Institute of Power Electronics
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• v.23 no.6
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• pp.433-439
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• 2018

This study considers the design of a submodule test circuit for the modular multi-level converter (MMC)-based HVDC systems. A novel submodule test circuit is proposed to provide not only an AC but also a DC component to the submodule current. However, the current waveforms depend on the capacitor voltages. Therefore, determining the capacitance value of the test circuit is important. Finding a proper capacitance value is easy when the proposed analysis method is used. Simulation and experimental results show the usefulness of the proposed method.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.9
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• pp.1566-1570
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• 2007

[ $SF_6$ ] gas circuit breakers are widely used for short circuit current interruption in EHV(Extra High Voltage) or UHV(Ultra High Voltage) power systems. To develop $SF_6$ gas circuit breakers, the arc resistance value is necessary to compare experimental results to numerical ones. The arc resistance value can be obtained from a breaking test with a $SF_6$ gas circuit breaker. The direct testing or synthetic testing facility is widely used to verify the breaking ability for $SF_6$ gas circuit breakers. We employed the simplified synthetic testing facility to test a $SF_6$ gas circuit breaker prototype. The arc resistance characteristic was measured and calculated under the various experimental conditions. This arc resistance value can be used for verifying the numerical results from arc simulation in a circuit breakers.

• Proceedings of the KIEE Conference
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• 1995.07b
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• pp.623-627
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• 1995

This paper describes analysis and optimization of Weil-Dobke synthetic testing circuit parameters, which is efficient and economical test method in high capacity AC circuit breaker. In this paper, analysis of synthetic short-circuit test circuit parameter proposed nondimensional factor that is reciprocal comparison value of circuit parameter and is not related to rated of circuit breaker, in particular, this study induce minimization of required energy of critical TRV generation specified in IEC 56 standards and present optimal design of synthetic short circuit testing facilities.

• Journal of the Korean Society of Physical Medicine
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• v.7 no.1
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• pp.125-135
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• 2012

Purpose : This study is designed to demonstrate the effects of circuit obstacle group gait training on walking ability and emotion in stroke patients. Methods : Twenty one patients with stroke were participated in this study. The subjects were divided into control group(n=10) and experimental group(n=11). Circuit obstacle group gait training consisted of walking around obstacles, walking over obstacles, walking up and down slopes and walking up and down stairs. Circuit obstacle group gait training was conducted five times per week, 1 hour per session, for 6 consecutive weeks. At pre-test and post-test, subjects were tested with 10 m walking test, timed up and go test, up and down 4 stairs test, depression and self esteem. Results : After 6 weeks of research, the experimental group showed statistically significant difference in all items when comparing prior to training and after training (p<.05), but the control group showed statistically significant difference in items other than depression and self esteem(p<.05). In the comparison between the two groups, the experimental group showed higher improvement than the control group in the 10 m walking test, timed up and go test, and up and down 4 stairs test, and there was statistically significant difference in decrease of degree in depression between the experimental group and control group(p<.05). Conclusion : This study have shown that circuit obstacle group gait training improves walking ability and emotion in stroke patients.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.7
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• pp.666-676
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• 1992

In this paper, algorithm and testable circuit to find all PSF(Pattern Sensitive Fault ) occured in RAM were proposed. Conventional test circuit and algorithm took much time in testing because consecutive test for RAM cells or f-dimensional memory struciure was not employed. In this paper, methodology for parallel RAM-testing was proposed by compensating additional circuit for test to conventional RAM circuit. Additional circuits are parallel comparator, error detector, group selector circuit and a modified decoder used for parallel testing. And also, the constructive method of Eulerian path to obtain efficient test pattern was performed. Consequently, If algorithm proposed in this paper Is used, the same operations as 32sxwor4 lines will be needed to test b x w=n matrix RAM. Circuit simulation was performerd, and 10 bits x :If words testable RAM was designed.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.3
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• pp.214-221
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• 2021

SiC MOSFETs require a faster and more reliable short-circuit protection circuit than conventional methods due to narrow short-circuit withstand times. Therefore, this research proposes a short-circuit protection circuit using a current-sensing circuit based on Rogowski coil. The method of designing the current-sensing circuit, which is a component of the proposed circuit, is presented first. The integrator and input/output filter that compose the current-sensing circuit are designed to have a wide bandwidth for accurately measuring short-circuit currents with high di/dt. The precision of the designed sensing circuit is verified on a double pulse test (DPT). In addition, the sensing accuracy according to the bandwidth of the filters and the number of turns of the Rogowski coil is analyzed. Next, the entire short-circuit protection circuit with the current-sensing circuit is designed in consideration of the fast short-circuit shutdown time. To verify the performance of this circuit, a short-circuit test is conducted for two cases of short-circuit conditions that can occur in the half-bridge structure. Finally, the short-circuit shutdown time is measured to confirm the suitability of the proposed protection circuit for the SiC MOSFET short-circuit protection.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.5
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• pp.82-89
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• 1993

In this paper, we proposed the autonomous algorithm of pseudo-exhaustive testing for the multi-level combinational logic circuits. For the processing of shared-circuit that existed in each cone-circuit when it backtracked the path from PO to PI of CUT at the conventional verification testing, the dependent relation of PI-P0 is presented by a dependence matrix so it easily partitioned the sub-circuits for the pseudo-exhaustive testing. The test pattern of sub-circuit's C-inputs is generated using a binary counter and the test pattern of I-inputs is synthesized using a singular cover and consistency operation. Thus, according to the test patterns presented with the recipe cube, the number of test pattrens are reduced and it is possible to test concurrently each other subcircuits. The proposed algorithm treated CUT's net-list to the source file and was batch processed from the sub-circuit partitioning to the test pattern generation. It is shown that the range of reduced ration of generated pseudo-exhaustive test pattern exhibits from 85.4% to 95.8% when the average PI-dependency of ISACS bench mark circuits is 69.4%.