• Journal of Korea Society of Industrial Information Systems
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• v.20 no.1
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• pp.1-7
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• 2015

In this paper, a 12-bit high resolution, power and area efficiency hybrid digital pulse width modulator (DPWM) with process and temperature (PT) calibration has been proposed for digital controlled DC-DC converters. The hybrid structure of DPWM combines a 6-bit differential tapped delay line ring-mux digital-to-time converter (DTC) schema and a 6-bit counter-comparator DTC schema, resulting in a power and area saving solution. Furthermore, since the 6-bit differential delay line ring oscillator serves as the clock to the high 6-bit counter-comparator DTC, a high frequency clock is eliminated, and the power is significantly saved. In order to have a simple delay cell and flexible delay time controllability, a voltage controlled inverter is adopted to build the deferential delay cell, which allows fine-tuning of the delay time. The PT calibration circuit is composed of process and temperature monitors, two 2-bit flash ADCs and a lookup table. The monitor circuits sense the PT (Process and Temperature) variations, and the flash ADC converts the data into a digital code. The complete circuits design has been verified under different corners of CMOS 0.18um process technology node.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.6 s.121
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• pp.639-647
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• 2007

This paper proposed the novel method that can realize the parallel coupled line(PCL) band-pass filter with directly coupled feeding structure by means of transforming the first and last PCL sections of the conventional PCL band-pass filter into K-inverters, then substituting T-type equivalence for K-inverter. The proposed method supplies simple design formulae and can considerably reduce time and efforts needed to optimize filter performance when compared to reported methods using external Q or equivalent parameters. On the basis of the proposed method, the band-pass filter using directly coupled feeding structure and having 18% fractional bandwidth was designed and fabricated. The validity of proposed method was proven by the measured result.

• Journal of Electrical Engineering and Technology
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• v.12 no.2
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• pp.643-653
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• 2017

The paper presents controller optimization algorithm for a 12-pulse voltage source converter (VSC) based high voltage direct current (HVDC) system. To get an optimum algorithm, three methods namely conventional-Zeigler-Nichols, linear-golden section search (GSS) and stochastic-particle swarm optimization (PSO) are applied to control of 12 pulse VSC based HVDC system and simulation results are presented to show the best among the three. The performance results are obtained under various dynamic conditions such as load perturbation, non-linear load condition, and voltage sag, tapped load fault at points-of-common coupling (PCC) and single-line-to ground (SLG) fault at input AC mains. The conventional GSS and PSO algorithm are modified to enhance their performances under dynamic conditions. The results of this study show that modified particle swarm optimization provides the best results in terms of quick response to the dynamic conditions as compared to other optimization methods.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.261-264
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• 2004

In this paper, we identify the memory effect of high power(125W) laterally diffused metal oxide-semiconductor(LDMOS) RF Power Amplifier(PA) by two tone IMD measurement. We measure two tone IMD by changing the tone spacing and the power level. Different asymmetric IMD is founded at different center frequency measurements. We propose the Tapped Delay Line-Neural Network(TDNN) technique as the modeling method of LDMOS PA based on two tone IMD data. TDNN's modeling accuracy is highly reasonable compared to the memoryless adaptive modeling method.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.11 no.4
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• pp.305-309
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• 2011

A sparse reconfigurable adaptive filter (SRAF) based on a photonic switch determines the appropriate time delays and weight values for an optical switch implementation of tapped-delay-line (TDL) systems. It is well known that the choice of switch delays is significantly important for efficiently implementing the SRAF. If the same values exist as calculating the sum of weight magnitudes for implementing the connection constraint required by the SRAF, conventional connection algorithm based on sequentially selection the maximum elements might not work perfectly. In an effort to increase the effectiveness of system identification, an upgraded connection algorithm used progressive calculation to obtain the better solution is considered in this paper. The performance of the proposed connection constraint algorithm is illustrated by computer simulation for a system identification application.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.8
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• pp.745-757
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• 1991

In this paper, the theoretical convergence property of the individual tap LMS algorithm for equaliz action if analyzed, and the pefomances over seeral multipath time vaing mobile radio channels are investigaed. The individual tap adjusting method of the tapped-elay line equalizer using LMS algorithm is proved to have Wiener optimum solution. It has more rapid convergence speed and lowe bit error rates than conventional Tdl LMS and gradient lattice equlizer in time invariant or time variant multipath channels.

• Proceedings of the Acoustical Society of Korea Conference
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• 1992.06a
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• pp.76-80
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• 1992

We consider the tapped-delay line (TDL) equalizer with the few calculation quantity and the simplity, the decision feedback equalizer (DFE) with the good property for interference, and lattice equalizer(LE) with high insensitivity to roundoff noise in mobile communication fading channel. The used adaptive algorithm is the LMS algorithm and RLS algorithm. In this paper, we have evaluated the performance of the TDL equalizer, the decision feedback equalizer, and lattice-structured equalizer, for the digital signal corrupted by the impulsive noise and the white gaussian noise under the fading channel environment. From the results of error performance analysis, it is confirmed that lattice-structured equalizer has better performance than DFE equalizer and TDL equalizer.

• Journal of the Korea Computer Industry Society
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• v.8 no.4
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• pp.263-268
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• 2007

It applied the linear tapped delay line structure to the least mean square algorithm and the recursive least square algorithm it investigated the mean square error characteristics of compensation algorithm. The purpose of this paper is to propose multi-tap update algorithm, which is superior to compensation capacity of data, and then compare and analyze it from the perspective of convergence characteristics at time invariant transmission channel and frequency selective fading channel.

• Journal of Power Electronics
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• v.12 no.2
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• pp.258-267
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• 2012

An interleaved single-stage AC/DC converter with a boost converter and an asymmetrical half-bridge topology is presented to achieve power factor correction, zero voltage switching (ZVS) and load voltage regulation. Asymmetric pulse-width modulation (PWM) is adopted to achieve ZVS turn-on for all of the switches and to increase circuit efficiency. Two ZVS half-bridge converters with interleaved PWM are connected in parallel to reduce the ripple current at input and output sides, to control the output voltage at a desired value and to achieve load current sharing. A center-tapped rectifier is adopted at the secondary side of the transformers to achieve full-wave rectification. The boost converter is operated in discontinuous conduction mode (DCM) to automatically draw a sinusoidal line current from an AC source with a high power factor and a low current distortion. Finally, a 240W converter with the proposed topology has been implemented to verify the performance and feasibility of the proposed converter.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.10B
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• pp.1707-1713
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• 2000

We have proposed a tunable optical ADM using a fiber-optic transversal filter which is composed of fiber couplers and metal-film coated fiber-optic tapped delay-lines with a flat spectral response in abroad range of wavelength. Simulation results show that the optical loss at the DROP and PASS wavelengths of the OADM is negligible and the wavelength tunability is 0.78${\mu}{\textrm}{m}$/ps for the unit time delay of 2 ps. In order to investigate the effects of wavelength drift of the imput optical signal on the OADM the loss at the DROP port and the crosstalks to the other ports have been calculated. The maximum bit rates have been calculated at 46.26 Gb/s for the input Gaussian pulse width of 10 ps.