• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.5A
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• pp.469-474
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• 2006

In this paper, we develop a method that derive the average sector throughput of HSDPA system. This proposed method reflects the effects of AMC, scheduling and multi-code transmission, and is performed by simple calculation procedures such as link budget analysis. Link budget table is used to estimate a cell coverage in general. We modify the link budget table in order to calculate C/I of the user according to the location of the user in CDMA packet system employing AMC. Furthermore, we utilize the proposed method to analyze the effects of scheduling and multi-code transmission.

• Science of Emotion and Sensibility
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• v.5 no.2
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• pp.63-72
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• 2002

In order to examine universal design, 1 have developed two analytical methodologies based on 3P(point) task analysis: structured task analysis and task matrix analysis. I also extracted nine universal design items, namely (1) adjustment, (2) redundancy, (3) specification and function transparency, (4) feedback and (5) error tolerance, (6) effective acquisition of information, (7) ease of understanding and judgment, (8) comfortable operation, and (9) continuity of information and operation. Structured task analysis is used to uncover problems in each of the tasks constituting a job for each functionally challenged condition of users, and solutions to the extracted problems are examined in terms of the above-mentioned nine universal design items. Task matrix analysis calls for the production of a table for each task in a job. In each table, nine items form the columns, and the horizontal rows list all disability types. Then, solutions are formulated for each cell formed by the intersecting columns and rows. Using these two analysis methods, 1 have conducted a verification experiment for the universal design of a public bus. The results of the research have enabled me to propose various ,solutions from a system-based perspective, instead of coming up with the superficial and isolated solutions which are normally produced when conventional analytical methods are used.

• Proceedings of the Korean Society for Emotion and Sensibility Conference
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• 2002.05a
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• pp.144-151
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• 2002

In order to examine universal desist I have developed two analytical methodologies based on 3P(point) task analysis: structured task analysis and task matrix analysis. I also extracted me universal design items, namely (1) adjustment (2) redundancy, (3) specification and function transparency, (4) feedback and (5) error tolerance, (6) effective acquisition of information, (7) ease of understanding and judgment (8) comfortable operation, and (9) continuity of information and operation. Structured task analysis is used to uncover problems in each of the tasks constituting a job for each functionally challenged condition of users, and solutions to the extracted problems are examined in terms of the above-mentioned nine universal design items. Task matrix analysis calls for the production of a table for each task in a job. In each table, nine items from the columns, and the horizontal rows list all disability types. Then, solutions are formulated for each cell formed by the intersecting columns and rows. Using these two analysis methods, T have conducted a verification experiment for the universal design of a public bus. The results of the research have enabled me to propose various solutions from a system-based perspective, instead of coming up with the superficial and isolated solutions which are normally produced when conventional analytical methods are used.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.11a
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• pp.1760-1762
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• 2010

본 논문에서 3치가산기와 승산기(multiplier)는 전류모드 CMOS에 의해서 구현된다. 첫째, 3치 T-gate를 집적회로 설계의 유효 가용성을 갖고 있는 전류모드 CMOS를 이용하여 구현한다. 둘째, 3치 T-gates를 이용해 회로가 유한체 GF (3)에 대하여 2변수 3치 가산표 (2-variable ternary addition table) 및 구구표 (multiplication table)가 실현되도록 구현한다. 마지막으로, 이러한 동작 회로들은 1.5 CMOS 표준 기술과 $15{\mu}A$ 단위전류(unit current) 및 3.3V 소스 전압 (VDD voltage)에 의해 활성화 된다. 활성화 결과는 만족할 만한 전류 특성을 나타냈다. 전류 모드 CMOS에 의하여 실행되는 3치가산기 및 승산기는 단순하며 와이어 라우팅(wire routing)에 대하여 정규적이고, 또한 셀 배열 (cell array)과 함께 모듈성 (modularity)의 특성을 갖고 있다.

• Journal of the Semiconductor & Display Technology
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• v.10 no.2
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• pp.73-81
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• 2011

We manufactured the inkjet printing system for the application into the nano Ag finger line interconnection process in Si solar cells. The home-made inkjet printer consists of motion part for XY motion stage with optical table, head part, power and control part in the rack box with pump, and ink supply part for the connection of pump-tube-sub ink tanknozzle. The ink jet printing system has been used to conduct the interconnection process of finger lines on Si solar cell. The nano ink includes the 50 nm-diameter. Ag nano particles and the viscosity is 14.4 cP at $22^{\circ}C$. After processing of inkjet printing on the finger lines of Si solar cell, the nano particles were measured by scanning electron microscope. After the heat treatment at $850^{\circ}C$, the finger lines showed the smooth surface morphology without micropores.

• The Journal of Korean Academy of Prosthodontics
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• v.45 no.2
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• pp.228-239
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• 2007

Statement of problem: Following tooth loss, the edentulous alveolar process of maxilla is affected by irreversible reabsorption process, with progressive sinus pneumatization leads to leaving inadquate bone height for placement of endosseous implants. Grafting the floor of maxillary sinus by sinus lifting surgery and augmentation of autologous bone or alternative bone material is a method of attaining sufficient bone height for maxillary implants placement and has proven to be a highty successful. Purpose: This study was undertaken to clarify the morphometric characteristics of inferior maxillary sinus and alveolar process for installation of implants. Material and method: Nineteen skulls (37 sinuses, 10M / 9F) obtained from the collection of the department of anatomy and cell biology of Hanyang medical school were studied. The mean age of the deceased was 69.9 years (range 44 to 88 years). The distance between alveolar border and inferior sinus margin at each tooth, the height of alveolar process and the thickness of cortical bone of the outer and inner table of alveolar process and the inferior wall of maxillary sinus were measured. Results and Conclusion: 1. The septum of inferior maxillary sinus were observe 28 sides (76.%) and located at the third molar (52.6%) and the second molar (26.3%). The deepest points of inferior border of maxillary sinus were located the first or second molar. The distance between alveolar margin and the deepest point of inferior maxillary sinus is $9.7{\pm}4.9mm$. 2. The length of the outer table of alveolar process were $4.9\sim28.2mm$ and the shortest point was between the first and the second molors. The thickness of them were $0.9\sim3.2mm$. The length of the inner table of alveolar process were $7.4\sim25.8mm$ and the shortest point was between the first and the second molars. The thickness of the were $0.9\sim4.6mm$. The results of this study are useful anatomical data for installing of maxillary implants.

• Journal of the Korea Society of Computer and Information
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• v.14 no.5
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• pp.183-193
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• 2009

Both On-Line Analytical Processing (OLAF) data cubes and Statistical Databases (SDBs) deal with multidimensional data sets. and both are concerned with statistical summarizations over the dimensions of the data sets. However, there is a distinction between the two that can be made. While SDBs are usually derived from other base data, OLAF data cubes often represent directly the base data. In other word, the base data of SDBs are the macro-data, whereas the core cubiod data in OLAF data cubes are the micro-data. The base table in OLAF is used to populate the data cube with values of the measure attribute, and each record in the base tables is used to populate a cell of the core cuboid. The fact that OLAF data cubes mostly represent the micro-data may make some records be absent in the base table. Some cells of the core cuboid remain empty, if corresponding records are absent in the base table. Wang and others proposed a method for securing OLAF data cubes against privacy breaches. They assert that the proposed method does not depend on specific types of aggregation functions. In this paper, however, it is found that their assertion on aggregate functions is wrong whenever any cell of the core cuboid remains empty. The objective of this study is to design an inference control process in OLAF data cubes which rectifying Wang's error.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.369-378
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• 2003

This paper presents design and VLSI implementations of a reassembly processor for ATM/AAL. The assembly processor is responsible for processing ATM cells from the receive physical interface. It controls the transfer of the AAL payload to host memory and performs all necessary SAR and CPCS checks. We propose the improved structure of cell identification algorithm and smart scatter method for host memory management. The proposed cell identification algorithm quickly locates the appropriate reassembly VC table based on the received VPI./VCI channel value in the ATM header. The cell identification algorithm also allow complete freedom in assignment of VCI/VPI values. The reassembly processor uses a smart scatter method to write cell payload data to host memory. It maintains the scatter operation and controls the incoming DMA block during scatter DMA to host memory. The proposed reassembly processor can perform reassembly checks on AAL. OAM cell. For an AAL5 connection, only CPCS checks, including the CRC32, are performed. In this paper, we proposed a practical reassembly architecture. The design of reassembly processor has become feasible using 0.6${\mu}{\textrm}{m}$ CMOS gate array technology.

• Journal of KIISE:Software and Applications
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• v.31 no.12
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• pp.1684-1690
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• 2004

This paper presents a method for classifier selection that uses distribution information of the training samples in a small region surrounding a sample. The conventional DCS-LA(Dynamic Classifier Selection - Local Accuracy) selects a classifier dynamically by comparing the local accuracy of each classifier at the test time, which inevitably requires long classification time. On the other hand, in the proposed approach, the best classifier in a local region is stored in the FSA(Feature Space Attribute) table during the training time, and the test is done by just referring to the table. Therefore, this approach enables fast classification because classification is not needed during test. Two feature space attributes are used entropy and density of k training samples around each sample. Each sample in the feature space is mapped into a point in the attribute space made by two attributes. The attribute space is divided into regular rectangular cells in which the local accuracy of each classifier is appended. The cells with associated local accuracy comprise the FSA table. During test, when a test sample is applied, the cell to which the test sample belongs is determined first by calculating the two attributes, and then, the most accurate classifier is chosen from the FSA table. To show the effectiveness of the proposed algorithm, it is compared with the conventional DCS -LA using the Elena database. The experiments show that the accuracy of the proposed algorithm is almost same as DCS-LA, but the classification time is about four times faster than that.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.115-122
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• 2004

In this paper, the multiple-valued adders and multipliers are implemented by current-mode CMOS. First, we implement the 3-valued T-gate and the 4-valued T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second we implement the circuits to be realized 2-variable 3-valued addition table and multiplication table over finite fields $GF(3^2)$, and 2-variable 4-valued addition table and multiplication table over finite fields $GF(4^2)$ with the multiple-valued T-gates. Finally, these operation circuits are simulated under $1.5\mutextrm{m}$ CMOS standard technology, $15\mutextrm{A}$ unit current, and 3.3V VDD voltage Spice. The simulation results have shown the satisfying current characteristics. The 3-valued adder and multiplier, and the 4-valued adder and multiplier implemented by current-mode CMOS is simple and regular for wire routing and possesses the property of modularity with cell array. Also, since it is expansible for the addition and multiplication of two polynomials in the finite field with very large m, it is suitable for VLSI implementation.