• 전기학회논문지
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• 제58권1호
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• pp.107-112
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• 2009

This paper describes design and fabrication issues of the SiP(System in Package) one-chip for a portable digital broadcasting receiver. It includes RF tuner chip, demodulator chip and passive components for the receiver system. When we apply the SiP one-chip technology to the broadcasting receiver, the system board size can be reduced from $776mm^2$ to $144mm^2$. SiP one-chip has an advantage that the area reduces more 81% than separated chips. Also the sensitivity performance advances -1dBm about 36 channels in the RF weak electric field, the power consumption reduces about 2mW and the C/N keeps on the same level.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권3호
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• pp.182-188
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• 2004

We demonstrate a $2.1\;{\times}\;1.0\;{\times}\;0.1cm^3$ sized compact transmitter using LTCC System-in-Package (SiP) technology for 60GHz-band wireless communication applications. For low-attenuation characteristics and resonance suppression of the SiP, we have proposed and demonstrated a coplanar double wire-bond transition and novel CPW-to-stripline transition integrating air-cavities as well as novel air-cavities embedded CPW line. The fabricated transmitter achieves an output of 13dBm at a RF frequency of 62GHz, an IF frequency of 2.4GHz, and a LO frequency of 59.6GHz. The up-conversion gain is 11dB, while the LO signal is suppressed with the image rejection mixer below -21.4dBc, and the image and spurious signals are also suppressed below -31dBc.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권4호
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• pp.255-261
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• 2005

With the advent of sub-90nm technologies, the system-on-chip (SoC) and system-in-package (SiP) are becoming the trend in delivering low-cost, low-power, and small-form-factor consumer electronic systems running at multiple GHz. The shortened transistor channel length reduces the transistor switching cycles to the range of several picoseconds, yet the time-of-flights of the critical on-chip and off-chip interconnects are in the range of 10 picoseconds for 1.5mm-long wires and 100 picoseconds for 15mm-long wires. Designers realize the bottleneck today often lies at chip-to-chip interconnects and the industry needs a good model to compute the inductance in these parts of circuits. In this paper we propose a new method for extracting accurate equivalent inductance circuit models for SPICE-level circuit simulations of system-on-chip (SoC) and system-in-package (SiP) designs. In our method, geometrical meshes are created and numerical methods are used to find the solutions for the electromagnetic fields over the fine meshes. In this way, multiple-GHz SoC and SiP designers can use accurate inductance modeling and interconnect optimization to achieve high yields.

• 마이크로전자및패키징학회지
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• 제29권1호
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• pp.1-6
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• 2022

The mobile device industry demands much higher levels of integration and lower costs coupled with a growing awareness of the complete system's configuration. A subsystem module package is similar to a board-level circuit that integrates a system function in a package beyond a System-in-Package (SiP) design. It is an advanced IC packaging solution to enhance the PDN and achieve a smaller form factor. Unlike a system-level design with a decoupling capacitor, a subsystem module package system needs to redefine the role of the capacitor and its configuration for PDN performance. Specifically, the design of package's form factor should include careful consideration of optimal PDN performance and the number of components, which need to define the decoupling capacitor's value and the placement strategy for a low impedance profile with associated cost benefits. This paper will focus on both the static case that addresses the voltage (IR) drop and AC analysis in the frequency domain with three specific topics. First, it will highlight the role of simulation in the subsystem module design for the PDN. Second, it will compare the performance of double-sided component placement (DSCP) motherboards with the subsystem module package and then prove the advantage of the subsystem module package. Finally, it will introduce three-terminal decoupling capacitor (decap) configurations of capacitor size, count and value for the subsystem module package to determine the optimum performance and package density based on the cost-effective model.

• 대한전자공학회논문지SD
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• 제45권10호
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• pp.59-65
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• 2008

UHF 대역과 13.56MHz를 동시에 지원하는 단일 패키지의 Multi band RFID 리더를 설계하고 SIP (System in Package)로 구현하였다. 제안된 리더 시스템은 UHF 대역에서 많이 사용되는 EPC Class1 Gen.2 표준과 HF대역인 13.56MHz에서 사용하는 ISO14443 A/B, ISO15693 프로토콜을 지원하고, RISC 코어에 탑재된 내장형 S/W에 의하여 동작 모드를 선택하도록 설계되었다. 제작된 시스템은 $40mm{\times}40mm$, 4 layer의 SiP 위에 구성되어 있으며 3.3V의 단일 공급전압으로 최대 210mA의 전류소모를 통해 13.56MHz의 경우 최대 5cm, UHF 대역의 경우 최대 20cm 인식거리를 실현하였다.

• 마이크로전자및패키징학회지
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• 제13권4호
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• pp.45-50
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• 2006

3D package의 SiP에서 구리의 via filling은 매우 중요한 사항으로 package밀도가 높아짐에 따라 via의 크기가 줄어들며 전기도금법을 이용한 via filling이 연구되어왔다. Via filling시 via 내부에 결함이 발생하기 쉬운데 전해액 내에 억제제, 가속제등 첨가제를 첨가하고 펄스-역펄스(PRC)의 전류파형을 인가하여 결함이 없는 via의 filling이 가능하다. 본 연구에서는 건식 식각 방법 중 하나인 DRIE법을 이용하여 깊이 $100{\sim}190\;{\mu}m$, 직경이 각각 $50{\mu}m,\;20{\mu}m$인 2가지 형태의 via을 형성하였다. DRIE로 via가 형성된 Si wafer위에 IMP System으로 Cu의 Si으로 확산을 막기 위한 Ta층과 전해도금의 씨앗층인 Cu층을 형성하였다. Via시편은 직류, 펄스-역펄스의 전류 파형과 억제제, 가속제, 억제제의 첨가제를 모두 사용하여 filling을 시도하였고, 공정 후 via의 단면을 경면 가공하여 SEM으로 관찰하였다.

• 마이크로전자및패키징학회지
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• 제15권1호
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• pp.7-18
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• 2008

This paper reviews the current development of an ultra-slim SiP for Radio Frequency (RF) application, in which three flip chips, additional passive components and Surface Acoustic Wave (SAW) filters are integrated side-by-side. A systematic investigation is carried out for the design optimization, process and reliability improvement of the package, which comprises several aspects: a design study based on the 3D thermo-mechanical finite element analysis of the packaging, the determination of stress, warpage distribution, critical failure zones, and the figuration of the effects of material properties, process conditions on the reliability of package. The optimized material sets for manufacturing process were determined which can reduce the number of testing samples from 75 to 2. In addition the molded underfilling (MUF) process is proposed which not only saves one manufacturing process, but also improves the thermo-mechanical performance of the package compared with conventional epoxy underfilling process. In the end, JEDEC's moisture sensitivity test, thermal cycle test and pressure cooker tests have also been carried out for reliability evaluation. The test results show that the optimized ultra-slim SiP has a good reliability performance.

• 전기학회논문지
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• 제57권12호
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• pp.2228-2233
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• 2008

This research paper aims to establish a test process of the AFE SiP chip. It measured the sensitivity, current consumption and power consumption both on the evaluation socket board and Catalyst load board. As a result, the sensitivity became deteriorated with an average of 0.2[dBm] at the channel 62 only, the current consumption increased to an average of 0.57[mA] and the power consumption increased to an average of 1.76[mW], But all characteristics incomes the tolerance of the measurement, it also keeps almost the same level. Therefore this design of the test process improved a valid design.

• 마이크로전자및패키징학회지
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• 제23권4호
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• pp.31-34
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• 2016

System In Package (SiP) is getting popular and momentum for the recent wearable, IoT and connectivity application apart from mobile phone. This is driven by market demands of cost competitive, lighter and smaller/thinner and higher performance. As one of many semiconducting assembly products, Leadframe product has been widely used for low cost solution, light/ small and thin form factor. But It has not been applied for SiP although Leadframe product has many advantages in cost, size and reliability performance. SiP is mostly based on laminate substrate and technically difficult on Leadframe substrate because of a limitation in SMT performance. In this paper, Leadframe based SiP product has been evaluated about key technical challenges in SMT performance and electrical shield technology. Mostly Leadframe is considered not available to apply EMI shield because of tie-bar around package edge. In order to overcome two major challenges, connection bars were deployed properly for SMT pad to pad and additional back-side etching was implemented after molding process to achieve electrical isolation from outer shield coating. This product was confirmed assembly workability as well as reliability.

• 한국전자파학회논문지
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• 제17권9호
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• pp.883-889
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• 2006

본 논문에서는 저온 소성 세라믹(Low-Temperature Co-fired Ceramic: LTCC)에 기초한 밀리미터파 RF SiP(System-in-Package) 모듈 응용을 위하여, CBCPW(Conductor Backed CPW) 전송선과 스트립 라인 대역 통과필터(BPF)에서 기생적으로 발생하는 공진 모드들과 40 GHz 전력 증폭기 모듈의 발진 현상을 분석하고 이를 제거하기 위한 방법들을 제안하였다. CBCPW 구조에서의 기생 구형 도파관(RWG) 모드는 비아의 간격을 줄여 공진 주파수를 높게 하여 동작 주파수 내에서 완전히 억제하였다. 스트립 라인 구조에서는 마주 보는 비아 중한 쪽을 제거하여 대각선으로 비아를 배치함으로써 완전히 제거하였다. CBCPW의 마이크로스트립 패치 공진기 모드들을 제거하기 위하여, 갭을 통한 커플링을 감소시키기 위해 갭에 인접하게 비아를 배치하였다. 그 결과 기생 공진 모드들이 완전히 제거되었다. 40 GHz 대역의 능동 증폭기 모듈의 경우, 상호 연결(interconnection)불연속 효과로 발생한 방사에 의한 인한 누설(cross talk)을 억제하기 위해, LTCC 기판 내부에 내장된 DC 전원 배선과 CPW 전송선의 고 격리 구조를 사용하여 발진 현상을 개선하였다.