• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.54-58
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• 2007

Development of high performance LTPS TFTs contributed to open up new SOP technology with various digital circuits integrated in display panels. This work introduces the current mode logic(CML) gate design method with which one can replace slow CMOS logic gates. The CML inverter exhibited small logic swing, fast response with high power consumption. But the power consumption became compatible with CMOS gates at higher clock speed. Due to small current values in CML, layout area is smaller than the CMOS counterpart even though CML uses larger number of devices. CML exhibited higher noise immunity thanks to its non-inverting and inverting outputs. Multi-input NAND/AND and NOR/OR gates were implemented by the same circuit architecture with different input confirugation. Same holds for MUX and XNOR/XOR CML gates. We concluded that the CML gates can be designed with few simple circuits and they can improve power consumption, chip area, and speed of operation.

• Journal of the Korea Society of Computer and Information
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• v.12 no.4
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• pp.249-256
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• 2007

AIn this paper, a new desist of LDI controller IC for general purpose is proposed for driving the LDI(LCD Driver Interface) controller in $4{\sim}9$ inches sized portable small-medium TFT-LCD(Thin Film Transistor addressed -Liquid Crystal Display) panel module. The designed LDI controller was verified on the FPGA(Reld Programmable Gate Array) test board, and was made the interactive operation with the commercial TFT-LCD panel successfully. The purpose of design is that it is standardized the LDI controller's operation by one LDI controller for driving all TFT-LCD panel without classifying the panel vendor, and size. The main advantage for new general-purpose LDI controller is the usage for the desist of all panel's SoG(System on a Glass) module because of the design for the standard operation. And in the previous method, it used each LDI controller for every LCD vendor, and panel size, but because a new one can drive all portable small-medium sized panel, it results in reduction of LDI controller supply price, and manufacturing cost of AV(Audio Video) board and panel. In the near future, the development of SoG IC(Integrated Circuit) for manufacturing more excellent functional TFT-LCD panel module is necessary. As a result of this research, the TFT-LCD panel can make more small size, and light weight, and it results in an upturn of domestic company's share in the world market. With the suggested theory in this paper, it expects to be made use of a basic data for developing and manufacturing for the SoG chip of TFT-LCD panel module.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.53-61
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• 2006

In high speed flash type or pipelining type A/D Converter, the faster sampling frequency is, the more the effect of DC reference fluctuation is increased by clock feed-through and kick-back. When we measure A/D Converter, further, external noise increases reference voltage fluctuation. Thus reference fluctuation reduction circuit must be needed in high speed A/D converter. Conventional circuit simply uses capacitor but layout area is large and it's not efficient. In this paper, a reference fluctuation reduction circuit using transmission gate is proposed. In order to verify the proposed technique, we designed and manufactured 6bit 2GSPS CMOS A/D converter. The A/D converter is based on 0.18um 1-poly 5-metal N-well CMOS technology, and it consumes 145mW at 1.8V power supply. It occupies chip area of $977um\times1040um$. Experimental result shows that SNDR is 36.25 dB and INL/DNL ${\pm}0.5LSB$ when sampling frequency is 2GHz.

• Journal of the Institute of Convergence Signal Processing
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• v.15 no.2
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• pp.70-75
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• 2014

Recently, the demand for high-integrated, low-powered, and high-powered SoC design has been increasing due to the multi-functionality and the miniaturization of digital devices and the high capacity of service informations. With the rapid evolution of the system, the required hardware performances have become diversified, the FPGA system has been increasingly adopted for the rapid verification, and SoC system using the FPGA and the ARM core for control has been growingly chosen. While the AXI bus is used in these kinds of systems in various ways, it is traditionally designed with AXI slave structure. In slave structure, there are problems with the CPU resources because CPU is continually involved in the data transfer and can't be used in other jobs, and with the decreased transmission efficiency because the time not used of AXI bus beomes longer. In this paper, an efficient AXI master interface is proposed to solve this problem. The simulation results show that the proposed system achieves reductions in the consumption clock by an average of 51.99% and in the slice by 31% and that the maximum operating frequency is increased to 107.84MHz by about 140%.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.9
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• pp.936-943
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• 2013

This work presents the design and measured results of the single channel automotive radar system for 76.5~77 GHz long range FMCW radar applications. The transmitter uses a commercial GaAs monolithic microwave integrated circuit(MMIC) and the receiver uses the down converter designed using 65 nm CMOS process. The output power of the transmitter is 10 dBm. The down converter chip can operate at low LO power as -8 dBm which is easily supplied from the transmitter output using a coupled line coupler. All MMICs are mounted on an aluminum jig which embeds the WR-10 waveguide. A microstrip to waveguide transition is designed to feed the embedded waveguide and finally high gain horn antennas. The overall size of the fabricated radar system is $80mm{\times}61mm{\times}21mm$. The radar system achieved an output power of 10 dBm, phase noise of -94 dBc/Hz at 1 MHz offset and a conversion gain of 12 dB.

• The Journal of the Korea Contents Association
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• v.8 no.6
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• pp.1-7
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• 2008

The paper is to solve the problem of existing sound system, which has difficulties of system organization and the increase of additional install cost and unfriendly interior. To solve the existing system, we drew the new sound system based on PLC and studied it. A transmitter and a receiver were designed using the PLC chip INT5500CS. Sound system was configured with a CD player that sound signals are sent from the transmitter and a speaker connected to the receiver. For analysis of characteristics of this system, a USBPre external sound card and Smaart Live 5 which is a PC-based sound measuring program were added. As a result of our experiment, the measured signal level is $2{\sim}3$[dB] lower than reference signal, latency is 16.69[ms] and the specific character of coherency is bad in high frequency band. Otherwise, this system transmits and receives signals over 90[%] in good condition as a result of measuring pink noise, frequency(1kHz), and phase, magnitude. In view of the result so far achieved, the system designed our team has excellent performance, it resolves defect of existing audio signal transmition system.

• Journal of the Korea Society of Computer and Information
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• v.14 no.2
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• pp.157-168
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• 2009

In this paper, a photovoltaic system is designed with a step up chopper and single phase PWM(Pulse Width Modulation) voltage source inverter. Where proposed Synchronous signal and control signal was processed by one-chip microprocessor for stable modulation. The step up chopper operates in continuous mode by adjusting the duty ratio so that the photovoltaic system tracks the maximum power point of solar cell without any influence on the variation of insolation and temperature because solar cell has typical voltage and current dropping character. The single phase PWM voltage source the inverter using inverter consists of complex type of electric power converter to compensate for the defect, that is, solar cell cannot be developed continuously by connecting with the source of electric power for ordinary use. It can cause the effect of saving electric power. from 10 to 20[%]. The single phase PWM voltage source inverter operates in situation that its output voltage is in same phase with the utility voltage. In order to enhance the efficiency of photovoltaic cells, photovoltaic positioning system using sensor and microprocessor was design so that the fixed type of photovoltaic cells and photovoltaic positioning system were compared. In result, photovoltaic positioning system can improved 5% than fixed type of photovoltaic cells. In addition, I connected extra power to the system through operating the system voltage and inverter power in a synchronized way by extracting the system voltage so that the phase of the system and the phase of single-phase inverter of PWM voltage type can be synchronized. And, It controlled in order to provide stable pier to the load and the system through maintaining high lurer factor and low output power of harmonics.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.6
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• pp.584-597
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• 2011

In this paper, low-loss and high-power RF SP6T switch chips are designed, fabricated and measured for GSM/EGSM/DCS/PCS applications using WIN Semiconductors 0.5 ${\mu}m$ pHEMT process. We utilized a combined configuration of series and series-shunt structures for optimized switch performance, and a common transistor structure on a receiver path for reducing chip area. The gate width and the number of stacked transistors are determined using ON/OFF input power level of the transceiver system. To improve the switch performance, feed-forward capacitors, shunt capacitors and parasitic FET inductance elimination due to resonance are actively used. The fabricated chip size is $1.2{\times}1.5\;mm^2$. S-parameter measurement shows an insertion loss of 0.5~1.2 dB and isolation of 28~36 dB. The fabricated SP6T switch chips can handle 4 W input power and suppress second and third harmonics by more than 75 dBc.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.15-22
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• 2005

This paper proposes an efficient structure which is able to perform self-detection and self-repair for faults in a digital system by imitating the structure of living beings. The self-repair system is composed of artificial cells, which have homogeneous structures in the two-dimension, and spare cells. An artificial cell is composed of a logic block based on multiplexers, and a genome block, which controls the logic block. The cell is designed using DCVSL (differential cascode voltage switch logic) structure to self-detect faults. If a fault occurs in an artificial cell, it is self-detected by the DCVSL. Then the artificial cells which belong to the column are disabled and reconfigured using both neighbour cells and spare cells to be repaired. A self-repairable 2-bit up/down counter has been fabricated using Hynix $0.35{\mu}m$ technology with $1.14{\times}0.99mm^2$ core area and verified through the circuit simulation and chip test.

• Journal of electromagnetic engineering and science
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• v.18 no.3
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• pp.188-198
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• 2018

In this study, we propose an approach for the design and satisfy the requirements of the fabrication of a small, lightweight, reliable, and stable ultra-wideband receiver for millimeter-wave bands and the contents of the approach. In this paper, we designed and fabricated a stable receiver with having low noise figure, flat gain characteristics, and low noise characteristics, suitable for millimeter-wave bands. The method uses the chip-and-wire process for the assembly and operation of a bare MMIC device. In order to compensate for the mismatch between the components used in the receiver, an amplifier, mixer, multiplier, and filter suitable for wideband frequency characteristics were designed and applied to the receiver. To improve the low frequency and narrow bandwidth of existing products, mathematical modeling of the wideband receiver was performed and based on this spurious signals generated from complex local oscillation signals were designed so as not to affect the RF path. In the ultra-wideband receiver, the gain was between 22.2 dB and 28.5 dB at Band A (input frequency, 18-26 GHz) with a flatness of approximately 6.3 dB, while the gain was between 21.9 dB and 26.0 dB at Band B (input frequency, 26-40 GHz) with a flatness of approximately 4.1 dB. The measured value of the noise figure at Band A was 7.92 dB and the maximum value of noise figure, measured at Band B was 8.58 dB. The leakage signal of the local oscillator (LO) was -97.3 dBm and -90 dBm at the 33 GHz and 44 GHz path, respectively. Measurement was made at the 15 GHz IF output of band A (LO, 33 GHz) and the suppression characteristic obtained through the measurement was approximately 30 dBc.