• Journal of electromagnetic engineering and science
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• v.18 no.1
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• pp.7-12
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• 2018

This article proposes an ultrahigh frequency band radio frequency identification (RFID) tag antenna for drug runout management that can be used in hospitals. The RFID tag antenna is designed to function as a sensor that alerts drug runout when a drug inside a drip chamber is completely consumed but does not work when a drug remains inside a drop chamber. A previously proposed 915 MHz dipole antenna, is too large to be attached to the drip chamber of a feeding bag. Moreover, the length of the dipole (L) should be increased for conjugate matching with an RFID chip. Therefore, the dipole antenna is downsized so that it can be attached to the drip chamber through a fine meander line structure coupling with a corrugate meander line. A transparent cover is added to enhance the grip force between the designed antenna and the drip chamber and to enable detachment. The dimensions of the completed antenna structure attachable to a drip chamber are 32.59 mm (height) and 13.5 mm (width). The gain reduction due to the decreased antenna length is enhanced. The fabricated antenna shows an average omni-directional read range of 10.65 m on a horizontal plane and has the function of sensing the presence of a drug.

• The Bulletin of The Korean Astronomical Society
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• v.35 no.1
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• pp.39.1-39.1
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• 2010

We are developing a CCD camera named CQUEAN (Camera for Quasars in Early Universe) to search for quasars at z > 7. CQUEAN has a 1024*1024 deep depletion CCD chip and will be attached to 2.1m Otto-Struve Telescope at McDonald Observatory, USA. Although commercial software for the CCD camera is provided by the vendor, we are going to develop our own software to control the other instruments as well, to carry out efficient observation. There are four major parts in our software: Instrument control part controls the camera and filter wheel to obtain imaging data. Quick look window is to display acquired imaging data for quick inspection. Telescope control part interfaces with Telescope Control System (TCS) to move the telescope and to get time or coordinate information. Finally, Observation scripting facility part carries out a series of short exposures in a batch. The whole software will be written in python on linux platform, using the instrument control software libraries provided by the vendors.

• Proceedings of the KIEE Conference
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• 1995.11a
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• pp.552-554
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• 1995

In long-haul high speed optical communications, the distance between a transmitter and a receiver depends on the amount of light coupled to a single mode optical fiber from the laser diode(LD) as well as the LD characteristic itself. And the transmitter module must have long lifetime. high reliability, and even simple structure. Such points have induced laser welding technique to be a first choice in opto-electronic module packaging because it can provide strong weld joint in a short time with very small coupling loss. In this paper, packaging considerations and characteristics for high speed LD modules are discussed. They include optical path design factors for larger aligning tolerance, and novel laser welding processes for component assembly. For low coupling loss after laser welding processes, the optical path for optimum coupling of a single mode optical fiber into the LD chip was designed with the GRIN lens system providing sufficiently large aligning tolerance both in the radial and axial directions. The measured sensitivity of the LD module was better than -33.7dBm(back to back) at a BER of $10^{-10}$ with a 2.5Gbps NRZ $2^{23}-1$ PRBS.

• Journal of the Korean Society for Precision Engineering
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• v.25 no.12
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• pp.39-46
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• 2008

Asymmetric glass lens core for portable projection optic system was designed and simulated. And it was machined by newly developed non-rotational ultra precision grinding method. With the designed lens data which optimized for multi-collimation, we generated the we core surface data. Mold pressing conditions analyzed by FEM. In the machining process, ground profile errors were compensated based on measured data, minimized feed rate and depth of cut. The deviations of machined core profile were acceptable level for glass mold press. Mold pressed glass array lens was coated with $SiO_2\;and\;Ta_2O_5$ for anti-reflection.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.1-8
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• 2005

In this paper, CMOS A/D converter with 6bit 2GSPS Nyquist input at 1.8V is designed. In order to obtain the resolution of 6bit and the character of high-speed operation, we present an Interpolation type architecture. In order to overcome the problems of high speed operation, a novel One-zero Detecting Encoder, a circuit to reduce the Reference Fluctuation, an Averaging Resistor and a Track & Hold, a novel Buffered Reference for the improved SNR are proposed. The proposed ADC is based on 0.18um 1-poly 3-metal N-well CMOS technology, and it consumes 145mW at 1.8V power supply and occupies chip area of 977um $\times$ 1040um. Experimental result show that SNDR is 36.25 dB when sampling frequency is 2GHz and INL/DNL is $\pm$0.5LSB at static performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.93-98
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• 2004

Serial ATA interface Is inexpensive comparatively and performance is superior. So it is suitable technology in demand that now require data transmission and throughput of high speed. This paper describes a design and implementation of Serial ATA Link layer about error detection and 8b/10b encoder/decoder for DC balance in frequency 150MHz. The 8b/10b Encoder is partitioned into a 5b/6b plus a 3b/4b coder. The logical model of the block is described by using Verilog HDL at register transistor level and the verified HDL is synthesized using standard cell libraries. And it is fabricated with $0.35{\mu}m$ Standard CMOS Cell library and the chip size is about $1500{\mu}m\;*\;1500{\mu}m$. The function of this chip has been verified and tested using testboard with FPGA equipment and IDEC ATS2 test equipment. It is used to frequency of 100MHz in verification processes and supply voltage 3.3V. The result of testing is well on the system clock 100MHz. The designed and verified each blocks may be used IP in the field of high speed serial data communication.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.1
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• pp.7-18
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• 2008

This paper reviews the current development of an ultra-slim SiP for Radio Frequency (RF) application, in which three flip chips, additional passive components and Surface Acoustic Wave (SAW) filters are integrated side-by-side. A systematic investigation is carried out for the design optimization, process and reliability improvement of the package, which comprises several aspects: a design study based on the 3D thermo-mechanical finite element analysis of the packaging, the determination of stress, warpage distribution, critical failure zones, and the figuration of the effects of material properties, process conditions on the reliability of package. The optimized material sets for manufacturing process were determined which can reduce the number of testing samples from 75 to 2. In addition the molded underfilling (MUF) process is proposed which not only saves one manufacturing process, but also improves the thermo-mechanical performance of the package compared with conventional epoxy underfilling process. In the end, JEDEC's moisture sensitivity test, thermal cycle test and pressure cooker tests have also been carried out for reliability evaluation. The test results show that the optimized ultra-slim SiP has a good reliability performance.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.29 no.10 s.241
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• pp.1289-1297
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• 2005

The flow in a microchannel is usually characterized as a low Reynolds number (Re) so that good mixing is quite difficult to be achieved. In this regard, we developed a novel chaotic micromixer, named Serpentine Laminating Micromixer (SLM) in the present study, Part 1. In the SLM, the higher level of chaotic mixing can be achieved by combining two general chaotic mixing mechanisms: splitting/recombination and chaotic advection. The splitting and recombination (in other term, lamination) mechanism is obtained by the successive arrangement of 'F'-shape mixing units in two layers. The chaotic advection is induced by the overall three-dimensional serpentine path of the microchannel. Chaotic mixing performance of the SLM was fully characterized numerically. To compare the mixing performance, a T-type micromixer which has the same width, height and length of the SLM was also designed. The three-dimensional numerical mixing simulations show the superiority of the SLM over the T-type micromixer. From the cross-sectional simulation results of mixing patterns, the chaotic advection effect from the serpentine channel path design acts favorably to realize the ideal lamination of fluid flow as Re increases. Chaotic mixing mechanism, proposed in this study, could be easily integrated in Micro-Total-Analysis-System, Lab-on-a-Chip and so on.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.5
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• pp.779-786
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• 2018

Ministry of oceans and Fisheries declared action plan for the electric fishing gear using real name in order to prevent overusing the fishing gear and to reduce discarded fishing gear. It is needed for a technique that can efficiently transmit the information including the type and location of the fishing gear and the user's real name to the fishing boat and the control center using IoT-based communication. In this paper, we propose the buoy-launched terminal equipment and ship-launched gateway equipment based on LoRa technology for effectively executing the electric fishing gear using real name. We design and fabricate to communicate 1(gateway):200(buoy) each other under 900 MHz ISM band by using SEMTECH SX1276 chip. Also, we experiment the test on the sea and analyze the test results to prove the implementation possibility of the proposed equipments for the electric fishing gear using real name.

• Journal of Korea Multimedia Society
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• v.16 no.1
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• pp.75-86
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• 2013

This paper presents a technique to implement embedded systems using interrupts of the one-chip microcontroller with many peripherals based on a multiple finite state machines model. The multiple finite state machine model utilizes the structure of FSMD used for hardware design and the features of flow control by interrupts. The main finite state machine corresponds to the main program and the sub-state machines corresponds to the interrupt subroutines. Therefore, interrupts from the peripherals can be processed immediately in the sub-state machines. The request and reply variables are used to interface between the finite state machines. Additional operating system is not necessary for the context switching between the main state machine and the sub-state machine, because the flow-control caused by interrupt can be replaced with the switching. An embedded system modeled on multiple finite state machine with ASM charts can be easily implemented by the conversion of ASM charts into C-language programs. This implementation technique can be easily adopted to the hardware oriented embedded systems because of the detail description of the model and the fast response to the interrupt events in the sub-state machine.